1.

General overview of
microprocessor
2. Memory interfacing
 What Microprocessor
is ?

Multipurpose, Programmable, Clock

driven Electronics device or IC
Basic Operations of
Microprocessor
Fetch: Microprocessor first brings the
instruction from Memory to CPU

Decode: Understands that

instruction

Execution: Performs the required

 Basic parts of a μP Based
System
• CPU (μP)
• Memory
• I/O devices
Bus
According to computer architecture, a bus is defined as a
single or set of wires that transfers data between
hardware components of a computer or between two separate
computers.

Types of Buses
Address Bus

Data Bus
Control Bus
 Generally contains one wire

 Generates control signals

 Some control signals are Read, Write

and Opcode fetch etc.
 Data Bus
A set of bidirectional wires

Sends or receives data or information

Number of wires used in a data bus is known as its

width

A microprocessor is generally known with its data bus

width

There are two types of data transfer; Serial

data transfer and Parallel data transfer
Address Bus

 A set of unidirectional wires are used

to select a device

 With n – digit numbering system we can

addressed maximum 2n number of houses

 Microprocessor having 16 bit address

bus can communicate with 216 or 65,536
numbers of devices
 Microprocessor Architecture
Contains various
registers that
store data
Registe temporarily during
ALU
r program
Array execution.
It performs
various arithmetic
and logical
functions
Control Unit

It provides necessary timing and

control signals during program
execution
 First Generation
Between 1971 – 1973
PMOS technology, non compatible with
Historical Background
Second Generation
TTL
During 1973
4 bit processors  16
NMOS technology  Faster speed,
pins
Higher density, Compatible with TTL
8 and 16 bit processors  40
4 / 8/ 16 bit processors  40 pins
pins Due to limitations of pins,
Ability to address large memory
signals are
spaces and I/O ports
multiplexed
Greater number of levels of
Third Generation subroutine nesting
During 1978 Better interrupt handling capabilities
HMOS technology  Faster speed,
Higher Intel 8085 (8 bit processor)
packing density
16 bit processors  40/ 48/ 64
pins Fourth Generation
Easier to program During 1980s
Dynamically relatable programs Low power version of HMOS
Processor has multiply/ divide technology (HCMOS)
arithmetic 32 bit processors
hardware Physical memory space 224 bytes = 16
More powerful Mb Virtual memory space 240 bytes = 1
interrupt handling Tb Floating point hardware
capabilities Supports increased number of
Flexible I/O port addressing addressing modes

Intel 8086 (16 bit Intel 80386

Fifth Generation Pentium processor)
MEMORY
A single Flip-Flop / Capacitor can store
one bit – 0 or 1

8 Flip-Flops together will form an 8-

bit Register

An 8-bit register can stores 8-bit or 1

Byte data
 A set of 8-bit register will form a
Memory
Ten 8-bit registers

i.e. 10 bytes of
memory

can store 10
bytes of data
10 x 8 bit memory
Or
10 byte memory
Accessing Memory or Memory Interfacing
11 Register 3
10 Register 2
01 Register 1
00 Register 0

0
0 A
0 1
1
2 to 4 Decoder
1
0 A
11 0
Calculate the address lines required for 10 K Byte
memory chip
1 K Byte = 1024 Byte of memory
Then 10 K Byte = 10 x 1024 Byte of memory

i.e. this memory chip has 10240 number of

8-bit registers (default register size is 8-bit)

Consider n number of address lines required

Then 2n = 10240
Or n = 13.32 ≈ 14

So 14 number of address lines required

Consider the number of address lines are 13. Calculate
the number of memory chips required to access total
address space if each memory chip is 1024 x 8 bit

Total addressable space using 13 address line is

213 Byte = 23 x 210 Byte = 8 x 1024 Byte = 8 K Byte

Each memory chip is 1024 x 8 bit

= 1024 Byte

Number of memory chip required

(8 x 1024)
=8
1024
Accessing memory can be summarized into the following
three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.

The microprocessor having N number of wires in its

address bus; uses part of the address bus to select the
chip and the remaining part goes through the address
decoder to select the register.

The control signals IO/M (to select I/O device

or memory), WR (enable writing) and RD (enable
reading) are used to activate the operation.
Consider a microprocessor having 16 bit Address
Bus

Maximum addressable memory space

216 Byte = 210. 26 Byte = 26 KByte = 64
Starting address will be
KByte
0000 0000 000
0
0000 1111 111
And last address will be 1
It is more convenient
1111 to use Hexadecimal
number
1111
In Hex code starting and last address will be
0000 H and
 Explain the memory address range

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH
 Draw the memory map to access 256
Byte memory using 16 bit address
A15 line
A14
A13
A12 C
A7
A11 S
A6
A10
A5
A9 256 Byte
A4
A8 Memory
A3
For addressing 256 Byte memory A2
we required only 8 address line (A0 to
A1
A7). Remaining 8 address lines (A8 to
A0
A15) is used of chip selection
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 7F00H
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH
Memory
Classification Memory

Primary Secondary
Memory Memory

Hard Disk,
RAM ROM
Floppy,
CD

Dynamic
Static RAM RAM Erasable Permanent

Flash Masked
EPROM EEPROM Memory ROM PROM
Random Access Memory (RAM)
Static RAM (SRAM)

• Store bit as voltage

• High speed
• More expensive
• High power consumption
Dynamic RAM(DRAM)
Dynamic RAM (DRAM)

• Stores bit as charge

• Low speed
• Less expensive
• Low power consumption
• Requires frequent
refreshing
 Read Only Memory (ROM)
Masked ROM
• Bit pattern is permanently masked

Programmable ROM (PROM)

• Program is burnt into the memory only once

Erasable PROM (EPROM)

• Program can be erased using UV ray

Electrically EPROM (EEPROM)

• Program can be erased using electrical signals

Flash Memory
• It can be erased and reprogrammed a million
times
1. Pin diagram of 8085
2. I/O interfacing
INTEL 8085 Pin Configuration
 The Address and Data Bus Systems

• The address bus has 8 signal lines A8 – A15 which

are unidirectional.
• The other 8 address bits are AD0 – AD7 multiplexed
(time shared) with the 8 data bits.
– So, the bits AD0 – AD7 are bi-
directional. During the execution of the
instruction, these lines carry the address
bits during the early part, then during
the late parts of the execution, they
carry the 8 data bits.
– In order to separate the address from
the data, we can use a latch to save the
value before the function of the bits changes.
Task

• Store a data 4FH (0100 1111) in the

memory location 2005H
FFFFH

4FH

2005H
microprocessor

0000H
Memory
Step 1

• First µP places the 16-bit address on

the address bus
• 2005H = 0010 0000 0000 0101
2 0 0
5

• It places 20H on the higher order address bus

A15 to A8
• And 05H on lower order address bus AD7 to
AD0
 A15 0
0
1
0 20H
0
0
0
µP A8
AD7
0
0
0
0
0 05H
0
1
0
AD0 1
 Step 2

• Lower order address bus [AD7 to AD0] are connected with a latch

• Latch is such a device whose input = output

when it is activated
• But when it is deactivated output does not

change with input

• ALE (Address Latch Enable) signal is

used to activate or deactivate the
latch
 A15 0
0
1
0 20H
0
0
0
µP A8
AD7
0
0
0
0 0
0 0
0 0 05H
Latch
0 0
1 1
0 0
AD0 EN 1
ALE 1
Step 3

• Once the lower order address is latched µP

places the data on the data bus [AD7 to AD0]

• And generate an appropriate control signal

to enable selected memory register

• Thus the data [4FH] is stored in memory

location 2005H
Demultiplex address/data bus
 Control Signals for Read/Write Operations

• IO/M = > 1 data transfer

between microprocessor and

peripherals (Input- Output device)

• IO/M = > 0 data transfer

between microprocessor and memory

• RD=> Active low => Read operation

• WR=> Active low => Write operation

Status Signals
Timing Diagram for Memory Write

To write data
4FH in the
memory
location 2005H
Timing Diagram for Memory Read

To read data
from the
memory
location 2005H
I/O DEVICE
Devices other than memory are known
as I/O devices or Input-Output Devices
Interfacing of I/O device with
8085
In peripheral I/O, device is identified by
an 8-bit address

In memory-mapped I/O, device is identified

by a 16-bit address
In 8-bit addressing mode
Maximum number of devices that can be
connected is 28 = 256

Address of the devices will be 00H, 01H,

… … , FFH

Both lower order 8 address bus (i.e. A0–A7) and

higher order 8 address bus (i.e. A8–A15) contains
the same 8-bit address
In 8-bit addressing mode
Only Accumulator is allowed for receiving
or transmitting data

Instruction to receive data from a device

with address C0H
IN C0H

Instruction to send data to a device with

address 12H
OUT 12H
Timing Diagram of ‘IN’ instruction

IN C0H

Memory Code

4125H DBH

4126H C0H
Timing Diagram of ‘OUT’ instruction

OUT 12H

Memory Code

4150H D3H

4151H 12H
 Device selection logic
Writing to an Output Port
(7EH)
A7
A6 OUT 7EH
A5
A4
A3
A2
A1
C
A0
S

IO / M
Data I/O Device Data
WR Bus Bus

A7 A6 A5 A4 A3 A2 A1 A0 Address

0 1 1 1 1 1 1 0 7EH
 Device selection logic
Reading an Input Port
(5DH)
A7
A6 IN 5DH
A5
A4
A3
A2
A1
C
A0
S

IO / M Data Data
Bus I/O Device Bus
RD

A7 A6 A5 A4 A3 A2 A1 A0 Address

0 1 0 1 1 1 0 1 5DH
 Absolute vs. Partial Decoding
In partial decoding some of the address
A7 lines are used. As a result the device has
A6 multiple address.

A5
A4
A3
A2
CS

IO / M
Data Data
Bus I/O Device Bus
RD

A7 A6 A5 A4 A3 A2 A1 A0 Address

0 1 1 1 1 1 X X 7CH – 7FH
Use of Decoder A7 A6 A5 A4 A3 A2 A1 A0 Address

Device 1 1 1 1 1 1 1 0 0 FC H
Device 2 1 1 1 1 1 1 0 1 FD H
Device 3 1 1 1 1 1 1 1 0 FE H
Device 4 1 1 1 1 1 1 1 1 FF H

A7
A6
A5
A4
A3
CS
11 A2

1
0 A
2 to 4 Decoder
1
0
1 A
0 0
0
In memory-mapped addressing mode

I/O device will be treated as a memory

register

Address of the devices will be 16-bit

All memory related instructions are

allowed Control signal IO/M pin should be

Memory Mapped
I/O
16-bit device address
Data transfer between any general-
purpose register and I/O port.
The memory map (64K) is shared
between I/O device and system
memory.
More hardware is required to decode
16- bit address
Arithmetic or logic operation can
be directly performed with I/O
data
Peripheral
Mapped
I/O
8-bit device address
Data is transfer only between accumulator
and I.O port
Independent of the memory map; 256
input device and 256 output device can be
connected
Less hardware is required to decode 8-bit
address
-Arithmetic or logical operation cannot be
directly performed with I/O data
1. Programming with 8085
2. Instruction set of 8085
 Programming with
8085
High Level Language Low Level Language

Machine Independent Machine Dependent

C, C++, Assembly Language,

Machine Language
JAVA
Internal Structure of
8085
 A is Accumulator – used to
perform arithmetic and logical
operations
 F is Flag register – not directly
accessible A Flag
 B, C, D, E, H, L are general
B C
purpose registers
 B-C, D-E, H-L can be used as 16-bit D E
register H L

SP
 SP is Stack PC
Pointer
 PC is Program Counter used by µP itself.
It stores the 16-bit address of the next
memory register to be executed
Flag Register
D0
S Z AC P
CY

S =1 Z =1
RESULT
P =1
EVEN NO. OF
NEGATIV 1’S
E IS ZERO

=0 =0
=0
RESULT IS ODD NO. OF
POSITIVE 1’S
NOT ZERO

AC =1
CARRY
CY =1
GENERATED CARR
BY D3 GENERATE
D
=0
=0
CARRY
OTHERWISE
NOT
GENERA
 Instruction Format
Each instruction has two parts
OPCODE: Operation to be performed

OPERAND: On which the operation to

be
performed

OPCODEMOV A, BOPERAND
 Instruction Byte Size
Number of registers required to store an instruction
in memory

HL 76 1 Byte
T

MVI B, 37H 06 37 2 Byte

STA 32 15 30 3 Byte
3015H
 Instruction Timing
Clock: A Clock is a square wave generator which is used
to synchronize various devices in the microprocessor and in
the system.

T State: Time period of the system Clock. (1 / frequency)

Instruction Cycle: Total time to execute a complete instruction

Machine Cycle: an instruction may be divided into

several parts like Opcode fetch, Memory read, Memory
write etc. Time to execute each part is known as Machine
Cycle.
Timing Diagram
Steps:
MVI A, 35H Opcode Fetch (4 T-state)
Memory Code Place the address 3010H in the address bus
0000 H XX Activate ALE signal
---- -- Activate Read signal
---- --
Copy Opcode 3E H in the data
3010 H 3E H
bus Memory Read (3 T-state)
3011 H 35 H
Place the address 3011H in the
---- -- address bus
---- --
Activate ALE signal
FFFF H XX
Activate Read signal
Copy Data 35 H in the data bus
 Timing
Diagram

MVI A, 35 H

Memory Code
3010 H 3E H
3011 H 35 H
 Steps:
Timing Diagram Opcode Fetch (4 T-state)
Place the address 3010H in the address bus
LXI H 2035H
 Activate ALE signal
Memory Code
 Activate Read signal
0000 H XX
Copy Opcode 21 H in the data bus
---- -- Memory Read (3 T-state)
---- --  Place the address 3011H in the
address bus
3010 H 21 H
 Activate ALE signal
3011 H 35 H  Activate Read signal
3012 H 20 H Copy Data 35 H in the data bus

---- -- Memory Read (3 T-state)

 Place the address 3012H in
FFFF H XX
the address bus
 Activate ALE signal
 Activate Read signal
8085 Instruction Set
 Addressing Mode
The different ways in which a source operand / data is
denoted in an instruction are known as addressing modes.
 Register Addressing
 Data stored in a register and that register is specified in the instruction

 Immediate Addressing
 Data itself is specified in the instruction

 Direct Addressing
 Data stored in memory and that address is specified in the instruction

 Register Indirect Addressing

 Specified register contains the address of the data

 Implicit Addressing
 No data is specified in the instruction
Types of
Instruction
1. Data Transfer Operation
2. Arithmetic Operation
3. Logical Operation
4. Branching & machine Control
Operation
• MOV Rd,
Rs
Rd: Destination
Rd Rs
Register Rs; Source
Register

Example:

MOV A,B
MOV C,H
MOV D,C
Addressing Mode:
Register Instruction Size: 1
• MVI Rd, <8-Bit
data> Rd
<8-Bit data>

Example:

MVI A, 54H
MVI C, 61H
MVI D,
8CH Addressing Mode: Immediate
Instruction Size: 2 Bytes
• LXI Rp, <16-Bit
data> Rp
Rp: Register <16-Bit data>
Pair

Example:

LXI H,5004H
LXI B,6021H
LXI D,840CH
Addressing Mode: Immediate
Instruction Size: 3 Bytes
• MVI M, <8 bit data>

• MOV R, M
R XXXXH
• MOV M, R
XX XX
H L
R: Register
M; Memory Register µP MEMORY

• Data transfer between microprocessor and a memory register

• Address of the memory register is stored in H-L register pair

Addressing Mode: Immediate / Reg.

Indirect Instruction Size: 2 Bytes / 1 Bytes
 39H

2003H
42 D 42H
42H 2004H
72H 2005H
Example: 20 04
H L

MEMORY
LXI H,2004H µP

MOV D,
M
• LDA <16 Bit Address>

• ST <16 Bit Address> STA

A 2500H

ACC

1600H 2500H
Mem
ACC

µP ory µP Memory

LDA 1600H Addressing Mode:

Direct Instruction Size: 3
Timing Diagram of ‘STA’ instruction
STA 526A
H

Memory Code
41FFH 32H
4200H 6AH
4201H 52H
 • LDAX • STAX
B B
• LDAX
D • STAX
D

ACC ACC

Memory Memory
B C B C
µP µP

Addressing Mode: Register

Indirect Instruction Size: 1 Bytes
• LHLD <16 Bit
• Address>
SHLD <16 Bit
SHLD 2080H
Address>

1660H 2080H
1661H 2081H

H L H L
Memory Memory

µP µP

LHLD 1660H
Addressing Mode:
Direct Instruction Size: 3
• XCHG
Exchange the contents of H-L with D-E register
pair

ab cd pq rs
D E D E

pq rs ab cd
H L H L

µP µP

Addressing Mode:
Register Instruction Size: 1
 ADDITION
• ADD
Acc R Acc
R

• ADD
M Acc MEMORY Acc
(Address from H-
L)

• ADI <8-BIT
Data>
Acc 8-Bit Data Acc
 ADDITION with
• ADC CARRY
R
Acc R CY Acc

• ADC
M
Acc MEMORY CY Acc
(Address from H-
L)
• ACI <8-BIT
Data>
Acc 8-Bit Data CY Acc
 SUBTRACTION
• SUB
Acc R Acc
R

• SUB
M Acc MEMORY Acc
(Address from H-
L)

• SUI <8-BIT
Data>
Acc 8-Bit Data Acc
 SUBTRACTION with
• SBB
BORROW
R
Acc R CY Acc

• SBB
M
Acc MEMORY CY Acc
(Address from H-
L)
• SBI <8-BIT
Data>
Acc 8-Bit Data CY Acc
• DAD 16 Bit Addition
Rp
H L Rp H L

 LXI H,1800H 18 00
XX XX
H L
B C

 LXI B,1200H 18 00 12 00
H L B C

 DAD B 2A
00 12 00
L B C
H


HLT
 Increment &
Decrement
• INR
R R
R
• DCR
R R R

• INX
Rp Rp Rp

• DCX
Rp Rp Rp
 • DAA
Decimal Adjust Accumulator
The DAA instruction is provided to correct the problem associated with
BCD (Binary Coded Decimal) addition

After an Addition instruction

1. If the lower nibble (4 bits) is greater than 9, or if AC=1, add 0110 (6) to
the lower 4 bits
2. If the upper nibble is greater than 9, or if CY=1, add 0110 (6) to the
upper 4 bits
Example
MVI A, 29H A = 29 H HEX BCD
29 0010 1001
ADI 18H A = 29H + 18H = 41H + 18 + 0001 1000
Aux. Carry = 1 41 0100 0001 AC=1
+ 6 + 0110
DAA A = 41H + 06H = 47H 47 0100 0111
 BCD Operation
The binary representation of the digits 0 to 9 is called BCD (Binary Coded
Decimal)

Digit BCD
Unpacked BCD 0 0000
In unpacked BCD, the lower 4 bits of the number represent 1 0001
the BCD number, and the rest of the bits are 0 2 0010

E x. 9 = 0000 1001 3 0011

4 0100
5 = 0000 0101
5 0101
6 0110
Packed BCD 7 0111
I n packed BCD, a single byte has two BCD number in it, one 8 1000
9 1001
Ein the59lower 4 bits,
= 0101 1001and
(notone in the
0011 upper 4 bits
1011)
x.
 Problem Associated with BCD Addition
BCD addition HEX addition

17 17
+ 28 45 + 28
(0100 0101) 3F (0011
1111)
To correct this problem, the programmer must add 6 (0110) to the low
digit: 3FH + 06H = 45H.

General rule: After addition

1. If the first digit is greater than 9, or if there is a carry generation in first
digit place, add 06H to the result
2. If the second digit is greater than 9, or if there is a carry generation in
second digit place, add 60H to the result
 AND Operation
• ANA R R

• ANA M
Acc /M/DATA Acc
• ANI <8-BIT
Data>
OR
• ORA R
Operation
• ORA M
Acc R/M/DATA Acc
• ORI <8-BIT
Data> XOR
• XRA R
Operation
• XRA M
Acc R/M/DATA Acc
• XRI <8-BIT
 Rotate Operation
• RLC (Rotate Accumulator
Left) X CY 1 CY

1 0 1 0 1 1 0 0 RLC 0 1 0 1 1 0 0 1

• RAL (Rotate Accumulator Left Through

Carry) X 1 CY
CY
1 0 1 0 RAL 0 1 0 1 1 0 0 X
1 1 0 0
 Rotate Operation
• RRC (Rotate Accumulator
Right) CY X 0 CY

1 0 1 0 1 1 0 0 RRC 0 1 0 1 0 1 1 0

• RAR (Rotate Accumulator Right Through

Carry) X 0 CY
CY
1 0 1 0 RAR X 1 0 1 0 1 1 0
1 1 0 0
 Compare
• CMP R
• CMP M
• CPI <8-Bit
When Result
Number> is —ve
CY Z
1 0
When Result
CY Z is +ve
0 0
Acc R/M/8-Bit No. When Result
CY Z is Zero
0 1
 Complement
• CMA
1’s complement of the content of the Accumulator

• CMC
Complement of the content of the Carry bit
Jump Instruction
2000H Instruction
1
2002H
2001H .Instruction
2
2003H .
2004H JMP 200AH
2005H
2006H
2007H .
2008H .
2009H .
200AH .
200BH .
200CH .
200DH .
200EH .
 Conditional Jump
• JP <16-Bit Address> jump when s = 0
• JM <16-Bit Address> jump when s = 1

• JZ <16-Bit Address> jump when z = 1

• JNZ <16-Bit jump when z = 0
Address>
• JPE <16-Bit Address> jump when P = 1
• JPO <16-Bit Address> jump when P = 0

• JC<16-Bit Address> jump when CY = 1

• JNC <16-Bit jump when CY = 0
Address>
 Some Special Instructions
• PCHL
Content of H-L pair are transferred to the program
counter

• NOP
No operation. Content of the program counter
is incremented by 1

• HLT
Microprocessor stops program execution until
an interrupt