FPGA-based (Xilinx) Embedded

System Design

Presented By:

Asst. Prof. A.Kamaraj

Date: 25th October, 2012

Technomeet on
Techknowledge Updation
Department of Electronics and Communication Engineering,
Mepco Schlenk Engineering College, Sivakasi
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Two Demonstrations
 Embedded System Design: Soft-processors MicroBlaze and
PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 2
 Integrated Circuits

ASIC

Gate Cell-Based Structured Full Custom

Arrays ICs ICs ICs

 All ICs are Logic

manufactured as
ASICs
Programmable Standard
Logic Devices
(PLDs) Logic
 Categorise by logic
functions
SPLDs CPLDs
(PALs) FPGAs

3
 Programmable Logic Device (PLD)

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

4
 Programmable Technologies

 One-time programmable
 Anti-fuse based
 Opposite of a regular fuse
 Normally an open circuit until a programming
current is forced on it (approx. 5 mA)
 Non-volatile reprogrammable
 Flash/EPROM based
 Limited reconfiguration cycles
 Reprogramming – slow
 Volatile reprogrammable
 SRAM based
 Unlimited number of reconfigurations possible
 Microseconds to milliseconds for reprogramming
5
 CPLD or FPGA?

 CPLD  FPGA
 Non-volatile  SRAM reconfiguration
 Combinational Logic  Excellent for computer
 Building block is the architecture, DSP, registered
macro cell, which contains designs
logic implementing  ASIC like design flow
disjunctive normal form  PROM required for non-volatile
expressions and more operation
specialized logic  Fair Sized Project
operations
Implementations
 Small student projects,
lower level courses

6
 Island style FPGAs

IOB CLB CLB CLB

Configurable
Logic
Block IOB CLB CLB CLB
Input
Output
Block IOB IOB IOB

Programmable
Interconnect
7
 Field-Programmable Gate Arrays (FPGAs)
• Fine-grained reconfigurable hardware
• Gate-Array: regular structure of “logic cells”, connected through an interconnection
network
• Configuration stored in SRAM, must be loaded on startup
EPROM

CSE, IITKGP 8
 Inside FPGAs
Embedded RAM IP Core
• Programmable Logic Blocks PLB

– Implement Combinational Routing

and Sequential Logic
• Modern FPGAs also contain
embedded SRAMs and other
IP cores to facilitate design
implementations

I/O Buffer

N
LUT/
RAM FF PLB Outputs

PLB Inputs

CSE, IITKGP 9
 An Example: 2-input LUT

x1 x1 x2 f1 x1
0 0 1
0/1 0 1 0 1
0/1 1 0 0 0
f 1 1 1 f1
0/1 0
0/1 (b) f 1 = x1x2+ x1x2 1
x2 x2

(a) Circuit for a two-input LUT (c) Storage cell contents

in the LUT

10
 LUT + Flip-flop

Select

Out
Flip-flop
In
1
In LUT D Q
2
In
3
Clock

11
Configurable Logic Block

Source: Smith, M.J.S., Application-Specific Integrated Circuits,Addison-Wesley, 1997.

CSE, IITKGP 12
 Available FPGAs
 Combined logic blocks and interconnects of traditional
FPGAs with embedded microprocessors and related
peripherals to form a complete “system on a programmable
chip”:
Xilinx Virtex-II PRO and Virtex-4 devices, include one
or more PowerPC processors embedded within the FPGA's
logic fabric
Atmel FPSLIC is another such device, which uses an
AVR processor in combination with Atmel's programmable
logic architecture

 An alternate approach is to make use of "soft" processor

cores that are implemented within the FPGA logic. These
cores include:
Xilinx MicroBlaze and PicoBlaze, the Altera Nios and
Nios II processors, as well as third-party (either commercial
or free) processor cores
13
FPGA vendors
Total 1999 PLD Market = $2.6B

Other
9%
Actel
7% Xilinx
35%
Lattice
16%

Altera
33%

Source: Xilinx University Program Workshop Notes

CSE, IITKGP 14
Xilinx FPGA Product Families
 Virtex-II (“Platform FPGA”, 10M gates)
 Virtex (1M gates), Virtex-E (3M gates)
 Spartan (low cost ASIC replacement)
 XC4000 (first FPGA family, now with
enhancements)

CSE, IITKGP 15
Altera FPGA Product Families
 APEX-II (up to 7M gates)
 APEX20K (up to 1.5M gates)
 Mercury (ASIC replacement, “ASSP”)
 FLEX 10K

CSE, IITKGP 16
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Two Demonstrations
 Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 17
 Xilinx Virtex-4 FPGAs
• Configuration memory: 4.7M to 50.8M bits of
RAM
• PLBs: 1,536 to 22,272
– 4 slices per PLB
• 2 LUTs & 2 FFs per slice
• 2 slices can operate as RAMs/SRs PC
• Block RAMs: 48 to 552 18K-bit dual-port
RAMs
– Also operate as FIFOs
• DSP cores: 32 to 512, each includes:
– 18x18-bit multiplier
– 48-bit adder & accumulator PC
• Up to 2 PowerPC processors

CSE, IITKGP 18
 Xilinx Spartan-3 Family
• The Spartan product is a cost reduced, high
volume FPGA. Most Spartan devices are a
close relative to another Xilinx product.
• There are several Spartan FPGA families:
– Spartan-II, Spartan-IIE (similar to Virtex).
– Spartan-3, Spartan-3E (similar to Virtex-4).

Presentation Name 19
 Spartan-3 Product Matrix
100X Density Range
Device XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
System Gates 50K 200K 400K 1000K 1500K 2000K 4000K 5000K

Logic Cells 1,728 4,320 8,064 17,280 29,952 46,080 62,208 74,880

Dedicated Multipliers 4 12 16 24 32 40 96 104

Block RAM Blocks 4 12 16 24 32 40 96 104

Block RAM Bits 72K 216K 288K 432K 576K 720K 1,728K 1,872K

Distributed RAM Bits 12K 30K 56K 120K 208K 320K 432K 520K

DCMs 2 4 4 4 4 4 4 4

I/O Standards 24 24 24 24 24 24 24 24

Max Single Ended I/O 124 173 264 391 487 565 712 784

50,000 to 5,000,000 System Gates

Presentation Name 20
 Spartan-3 FPGA Board

Xilinx Devices: Spartan-3 (XC3S200)

Clocks: 50 MHz crystal clock oscillator

Memory: 256Kx16 ISSI - 10 ns SRAM devices

 Spartan-3 Starter Kit
Connectors and Interfaces
1. Xilinx Spartan-3 FPGA with twelve 18-bit
multipliers, 216Kbits of block RAM, and
up to 500MHz internal clock speeds
2. -200, -400, and -1000 versions available
3. On-board 2Mbit Platform Flash (XCF02S)
4. 8 slide switches, 4 pushbuttons, 9 LEDs,
and 4-digit seven-segment display
5. Serial port, VGA port, and PS/2
mouse/keyboard port
6. Three 40-pin expansion connectors
7. Three high-current voltage regulators
(3.3V, 2.5V, and 1.2V)
8. 1Mbyte on-board 10ns SRAM (256Kb x
32)
 Digilent Spartan-3 Hardware Development Module
Web link to Spartan 3 documentation - (www.digilentinc.com)
Voltage JTAG FPGA configuration bitstream
regulator download cable
FPGA config done LED 2Mbit platform flash
config PROM
VGA port

Push button switch

(forces FPGA
Expansion
reconfiguration)
connectors
Power In
(& regulators) Xilinx Spartan-3 FPGA
[XC3S200-4ft256]
Poweron indicator
LED
PS/2 port
Serial port
RS-232
8 LEDs [ld(7:0)]
Secondary
4 Push button switches [btn(3:0)] oscillator skt Four 7-segment displays
[common led connections,
8 Toggle Switches [sw(7:0)] separate anodes, all low
CSE, IITKGP
lockSysAsgnInstr asserted] 23
 Xilinx Design Tools

 Xilinx’s ISE

 Xilinx’s Platform Studio

CSE, IITKGP 24
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Two Demonstrations
 Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 25
 Xilinx’s ISE Design Flow

CSE, IITKGP 26
 ISE Design flow

Specification
Specification Synthesis
Synthesis
Generic
HDL or Netlist
Schematics
Technology
Technology
Mapping
Mapping

Device
Device Place Dependent
Device Place and
and Netlist
Configuration
Configuration Route
Route
Bit stream
27
 FPGA tool flow

HDL
(VHDL /  Hardware design is traditionally done by
Verilog)
modeling the system in a hardware
description language
Synthesize
 An FPGA “compiler” (synthesis tool)
generates a netlist
Netlist  which is then mapped to the FPGA
technology
Map  the inferred components are placed on the
chip
Place
 and the connecting signals are routed
Route through the interconnection network

Bitstream

28
 HDL Synthesis

HDL process(clk, reset)

(VHDL / begin
Verilog)
if reset = ‚1‘ then
output <= ‚0‘;
elsif rising_edge(clk) then
Synthesize output <= a XOR b;
end if;
end process;
Netlist

Map

Register
Place
a D Q output

Route b

clk
clear

Bitstream reset

29
 Technology Mapping
Register
HDL
a D Q output
(VHDL / 
b
Verilog)
clk
clear
Synthesize
reset

Netlist

Map

Place

Route

Bitstream

30
 Place & Route

HDL
(VHDL /
Verilog)

Synthesize

Netlist

Map

Place

Route

Bitstream

31
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 32
 Embedded Systems
• An embedded system is a computing system
(other than a general-purpose computer) with
the following general characteristics
– Single-functioned
• Typically, is designed to perform predefined function
– Tightly constrained
• Tuned for low cost
• Single-to-fewer components based
• Performs functions fast enough
• Consumes minimum power
– Reactive and real-time
• Must continually monitor the desired environment and
react to changes
– Hardware and software co-existence

CSE, IITKGP 33
 Embedded Systems
• Examples:
– Communication devices
• Wired and wireless routers and switches
– Automotive applications
• Braking systems, traction control, airbag release
systems, and cruise-control applications
– Aerospace applications
• Flight-control systems, engine controllers, auto-
pilots and passenger in-flight entertainment
systems
– Defense systems
• Radar systems, fighter aircraft flight-control
systems, radio systems, and missile guidance
systems

CSE, IITKGP 34
 Current Technologies

• Microcontroller-based systems
• DSP processor-based systems
• ASIC technology
• FPGA technology

CSE, IITKGP 35
 Embedded Design in an FPGA

• Embedded design in an FPGA consists of

the following:
– FPGA hardware design
– C drivers for hardware
– Software design
 Embedded CPUs
 PowerPC 405 (hard core)
 32 bit embedded PowerPC RISC architecture
 Up to 450 MHz
 2x16 kB instruction and data caches
 Memory management unit (MMU)
 Hardware multiply and divide
 Coprocessor interface (APU)
 Embedded in Virtex-II Pro and Virtex-4
 PLB and OCM bus interfaces

 MicroBlaze (soft core)

 32 bit RISC architecture
 2 64 kB instruction and data caches
 Barrel Shifter
 Hardware multiply and divide
 OPB and LMB bus interfaces
Images by Xilinx

 Others
 NIOS (Altera), ARM, PicoBlaze [soft core; 8-bit] (Xilinx), ...

37
 Processor in FPGA
 Softcore microprocessor: using FPGA resources only
 Synthesize and compiling need: tools are very important
 Xilinx offering: MicroBlaze & PicoBlaze
 Altera offering: NIOS

 Hardcore microprocessor: hardwired in FPGA architecture

 3rd party tools
 Xilinx: (Virtex II Pro) PowerPC from IBM
 Altera: (Excalibur APEX) ARM922T from ARM

38
 FPGA Soft Core Processors

 Soft-core Processor
 HDL description
HDL
 Flexible implementation Description
 FPGA or ASIC

 Technology independent
 A soft processor is very FPGA ASIC
configurable
 How to optimize the implementation
without too many variants?
 Avoid too much low-level and only do Spartan 3 Virtex 2 Virtex 4
it when necessary
 MicroBlaze is a mixture of very
detailed implementation and pure
RTL code

39
 FPGA Soft Core Processors

 Soft Core Processors can have configurable options

 Datapath units

 Cache

 Bus architecture

 Current commercial FPGA Soft-Core Processors

 Xilinx Microblaze

 Altera Nios

FPU
μP MAC

Cache

FPGA

40
 Embedded Processors

 Hard core  Soft core

 Faster  Slower
 Fixed position  Can be placed anywhere
 Few devices  Applicable to many devices

 Virtex-4 Processors:

Embedded Core Max Clock Block

Slices PLBs
Processor Type Frequency RAMs
PowerPC Hard 222 MHz 1000 250 9
MicroBlaze
PowerPC
MicroBlaze
PicoBlaze
Microblaze Soft 180 MHz 940 235 9
Picoblaze Soft 221 MHz 333 84 3
Picoblaze
Soft 233 MHz 274 69 3
(optimized)

41
 IP Cores
 IP Cores are pre-designed HDL codes optimised for
a particular functions
 Accepts parameters, and generates behavioural &
optimised HDL structures
 Design reuse, ease of design (eg. coregen) for FPGA,
outsourcing

42
 PowerPC-based Embedded Design
RocketIO
Dedicated Hard IP
DSOCM ISOCM
BRAM PowerPC BRAM Flexible Soft IP
405 Core IBM CoreConnect™
DCR Bus on-chip bus standard
Instruction Data
PLB, OPB, and DCR

PLB OPB

Arbiter
Arbiter

Bus
Processor Local Bus On-Chip Peripheral Bus
Bridge

e.g.
Hi-Speed Memory GB On-Chip
UART GPIO
Peripheral Controller E-Net Peripheral

Off-Chip ZBT SRAM Full system customization to meet

Memory DDR SDRAM performance, functionality, and
SDRAM cost goals
Source: Xilinx
CSE, IITKGP 43
 MicroBlaze-based Embedded Design

I-Cache

BRAM Local Memory MicroBlaze

BRAM Flexible Soft IP
Configurable
Bus 32-Bit RISC Core Sizes
D-Cache Possible in Dedicated Hard IP
BRAM Virtex-II Pro PowerPC
405 Core
Instruction Data
LocalLink™ OPB
Arbiter
FIFO Channels PLB

Arbiter
Bus
On-Chip Peripheral Bus Bridge
Processor Local Bus
0,1…….32
e.g.
Hi-Speed Memory GB
Custom Custom Peripheral Controller E-Net

Functions Functions
10/100 On-Chip
UART
E-Net Peripheral

Off-Chip FLASH/SRAM
Memory
Source: Xilinx
CSE, IITKGP 44
What is Microblaze?

 Soft core processor,

implemented using general
logic primitives
 32-bit Harvard RISC
architecture
 Supported in the Xilinx
Spartan and Virtex series of
FPGAs
 Customizability of the core
makes it challenging while
opening up vistas for kernel
configurations
CSE, IITKGP 45
Microblaze
 32-bit soft processor solution
 soft core, meaning that it is implemented
using general logic primitives rather than a
hard, dedicated block in the FPGA
 MicroBlaze soft core licensed as part of the
Xilinx Embedded Development Kit (EDK)
 Complete embedded development solution
that includes:
 A library of peripheral IP cores,
 The award-winning Xilinx Platform Studio tool
suite for intuitive hardware system creation
 A Built-On Eclipse software development
environment
 GNU compiler, debugger and more.
 The MicroBlaze processor is also supported
by third party development tools and Real
Time Operating Systems (RTOS)

CSE, IITKGP 46
 MicroBlaze v4.00 Block Diagram
Enhanced CPI

Multiplier

FPU

Enhanced
Debug

User Configurable Increased Clock

Options Frequency
IXCL_M – Instruction side Xilinx Cache Link Master IOPB – Instruction side On-chip Peripheral Bus
IXCL_S – Instruction side Xilinx Cache Link Slave DOPB – Data side On-chip Peripheral Bus
DXCL_M – Data side Xilinx Cache Link Master ILMB – Instruction side Local Memory Bus
DXCL_S – Data side Xilinx Cache Link Slave DLMB – Data side Local Memory Bus
MFSL – Master Fast Simplex Link Bus IF – Bus Interface
SFSL – Slave Fast Simplex Link

47
 PicoBlaze KCPSM3 processor

 Author: Ken Chapman, Xilinx; chapman@xilinx.com

 VHDL Core with assembler: free from www.xilinx.com
 Main parameters:
 8 bit CPU, 1 BRAM 1024x18 for program, only 96 slices (5% of
xc3s200)
 16 registers, Scratch pad memory 64 byte, 8bit I/O bus, 8bit port
address
 all instructions take constantly 2 clock cycles, 1 level of interrupt
 KCPSM3 includes Assembler, RS232 macros and uart_clock demo.
 Optimized for Virtex E, Virtex 2, and Spartan 3
 Our design is reusing parts of Ken’s uart_clock demo
 We add inter-processor connect, VGA support and Floating point
HW
 We add hazard free access to DP BRAM from Master and Worker
PicoBlaze

48
 PicoBlaze KCPSM3 processor

 Xilinx PicoBlaze is a compact, capable, and cost-effective

fully embedded 8-bit RISC microcontroller core optimized
for the Xilinx Spartan™-3, Virtex™-II, Virtex-II Pro™ and
Virtex-4 FPGAs and CoolRunner™-II CPLDs
 Predictable performance, always two clock cycles per
instruction, up to 200 MHz or 100 MIPS in a Virtex-4™ FPGA
and 88 MHz or 44 MIPS in a Spartan-3 FPGA
 16 byte-wide general-purpose data registers
 1K instructions of programmable on-chip program store,
automatically loaded during FPGA configuration
 Byte-wide Arithmetic Logic Unit (ALU) with CARRY and
ZERO indicator flags
 64-byte internal scratchpad RAM
 256 input and 256 output ports for easy expansion and
enhancement
 Automatic 31-location CALL/RETURN stack
 Assembler, instruction-set simulator support

49
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Two Demonstrations
 Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 50
Traditional Embedded System

Power Supply
Ethernet Audio CLK
CLK
MAC Codec

GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memory Proc. custom
CLK Controller IF-logic

SRAM SRAM SRAM Display

SDRAM SDRAM Controller
 Next Step...

Power Supply
Ethernet Audio CLK
CLK
MAC FPGA Codec

GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memory Proc. custom
CLK Controller IF-logic

SRAM SRAM SRAM Display

SDRAM SDRAM Controller
Configurable System on a Chip (CSoC)

Audio
Codec EPROM

Power Supply

L
C

SRAM SRAM SRAM SDRAM SDRAM

Reconfigurable System on a Chip (SoC)

How to build such a system ?

1. Overview:
 Xilinx EDK / MicroBlaze Soft CPU core
 Design- / Tool-Flow

2. Demonstration:
 Create a simple system
 Implement the system on a Xilinx Spartan-III FPGA
Soft CPU Core: MicroBlaze (Xilinx Inc.)
 MicroBlaze: Architecture & Features
Architecture

OPB

LMB

Features • RISC
• Thirty-two 32-bit general purpose registers
• 32-bit instruction word with three operands and two addressing modes
• Separate 32-bit instruction and data buses OPB (On-chip Peripheral Bus)
• Separate 32-bit instruction and data buses LMB (Local Memory Bus)
• Hardware multiplier (in Virtex-II and subsequent devices)
 MicroBlaze: Bus Configurations

1.

MicroBlaze core
2.

3.

4.

• LMB: Memory Controller (BRAMs) 5.

• OPB: Ext. Memory Ctrl., Interrupt Ctrl., UART, Timer,
Watchdog, SPI, JTAG-UART, etc.
6.
 Bus Configuration 3

• Instructions and data from internal BRAMs (fast)

• Data from external memory
 Xilinx Platform Studio Design Flow using
MicroBlaze

CSE, IITKGP 59
 Embedded Development
Tool Flow Overview
Standard Embedded SW Standard FPGA HW
Development Flow Development Flow
C Code VHDL/Verilog

Compiler/Linker Synthesizer
(Simulator) Simulator

Object Code Place & Route

? ?
CPU code in CPU code in
off-chip on-chip
memory memory Download to FPGA

Download to Board & FPGA

Debugger

Source: Xilinx
CSE, IITKGP 60
 EDK
• The Embedded Development Kit (EDK) consists of
the following:
– Xilinx Platform Studio – XPS
– Base System Builder – BSB
– Create and Import Peripheral Wizard
– Hardware generation tool – PlatGen
– Library generation tool – LibGen
– Simulation generation tool – SimGen
– GNU software development tools
– System verification tool – XMD
– Virtual Platform generation tool - VPgen
– Software Development Kit (Eclipse)
– Processor IP
– Drivers for IP
– Documentation
• Use the GUI or the shell command tool to run EDK
 EDK Tools
• EDK = Embedded Development Kit
• XPS = Xilinx Platform Studio
• PlatGen = Platform Generator
– Uses an MHS file to create an implementation netlist of a
bus-based subsystem
• LibGen = Library Generator
– Uses the MHS and MSS files, software libraries, and source
files to generate an executable image
• SimGen = Simulation Generator
– Uses the MHS file to generate a simulation environment
including simulation models, HDL wrappers, simulation
scripts, etc.
• XMD = Xilinx Microprocessor Debugger
– Provides communication between the GDB and the
processor
• CreateIP = Create/Import Peripheral Wizard
– Helps you create your own peripherals and import them into
EDK compliant repositories or Xilinx Platform Studio (XPS)
projects
 EDK Files

• MHS = Microprocessor Hardware

Specification
• MSS = Microprocessor Software
Specification
• MPD = Microprocessor Peripheral
Description
• PAO = Peripheral Analyze Order
• BBD = Black-Box Definition
• MDD = Microprocessor Driver Description
• BMM = BRAM Memory Map
Design Flow: Hardware I
Hardware

Platform Definition
(peripherals, configuration,
connectivity, address space)

*.mhs

Generate
Netlist

 EDK / Xilinx Platform Studio

Design Flow: Hardware II
Hardware

Platform Definition
(peripherals, configuration,
connectivity, address space)

*.mhs

Generate
Netlist
ISE
XPS

Platform Ext. *.ucf

Proj.Nav. / VHDL

Generate *.bit
Bitstream

 EDK: Embedded Development Kit

 XPS: Xilinx Platform Studio
 ISE: Integrated Software Environment
 MHS: Microprocessor Hardware Specification
Design Flow: Software
Hardware Software

*.c *.asm
Platform Definition Gen.
(peripherals, configuration, Libs
connectivity, address space) *.h

*.mhs
Compile
Generate
&
Netlist
Link
ISE
XPS

Platform Ext. *.ucf *.elf

Proj.Nav. / VHDL

Generate *.bit
Bitstream

 EDK: Embedded Development Kit

 XPS: Xilinx Platform Studio
 ISE: Integrated Software Environment
 MHS: Microprocessor Hardware Specification
Design Flow: Combine HW + SW
Hardware Software

*.c *.asm
Platform Definition Gen.
(peripherals, configuration, Libs
connectivity, address space) *.h

*.mhs
Compile
Generate
&
Netlist
Link
ISE
XPS

Platform Ext. *.ucf *.bmm

*.elf
Proj.Nav. / VHDL

Update
Generate *.bit Bitstrea
Bitstream m

*.bit
 EDK: Embedded Development Kit
 XPS: Xilinx Platform Studio
 ISE: Integrated Software Environment
 MHS: Microprocessor Hardware Specification
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 Two Demonstrations
 Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

CSE, IITKGP 68
 Xilinx Spartan 3E kit

CSE, IITKGP 69
Demonstration:
An application using PicoBlaze: [Using Xilinx ISE
tool]

70
Demonstration…
 That’s all about FPGA-based(Xilinx)
Embedded System Design

CSE, IITKGP 72
 For more information...
Xilinx EDK & MicroBlaze: www.xilinx.com/edk
Embedded Processing:

http://www.xilinx.com/products/design_resources/proc_central/index.htm

Xilinx Platform Studio user guide: http://www.xilinx.com/ise/embedded/ps_ug.pdf

MicroBlaze user guide: http://www.xilinx.com/bvdocs/userguides/ug133.pdf

PicoBlaze user guide:

http://www.xilinx.com/bvdocs/userguides/ug129.pdf

http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm

Spartan Kit Data sheet: http://www.xilinx.com/bvdocs/publications/ds099.pdf

 Questions?

CSE, IITKGP 74