BM 3551 – EMBEDDED SYSTEMS

AND IOT

UNIT 1 : INTRODUCTION TO EMBEDDED

SYSTEM DESIGN

Topic : CPU Bus, Bus Organization, Bus Protocols

Ms. S. Indu
AP / BME
Bus Organization
 Data Bus
Data bus is a computer subsystem that facilitates the exchange of information
between various components on a motherboard or system board or between
separate computers. This involves moving information to and from the system's
RAM or the CPU.

Size and Speed:

• Width: Measured in bits (e.g., 8-bit, 16-bit, 32-bit), the width determines the
amount of data transferred in a single operation. A wider data bus allows for
faster data transfer but also requires more complex hardware and consumes
more power.
Examples of Data Bus Widths:
 8-bit: Often used in simpler embedded systems for low data volume and cost-
efficiency.
 16-bit: Commonly found in microcontrollers, offering a balance between data
transfer rate and complexity.
 32-bit: Used in more advanced embedded systems for higher performance
applications where data processing needs are significant.
• Speed: The data bus operates at a specific clock frequency, which along with
the width, determines the overall data transfer rate. This is similar to how
lane width and speed limit on a highway affect traffic flow.

Data Transfer Modes:

There are two main ways data travels on the data bus:

• Uni-directional: In some cases, the data bus is one-way, carrying data either
from the CPU to memory/peripherals (write operation) or vice versa (read
operation). This is simpler to implement but might limit performance.
• Bi-directional: A more common approach, the data bus allows data to flow
in both directions. The CPU can both read data from memory/peripherals
and write data to them. This offers more flexibility but requires additional
control logic to manage the direction of data flow.
Address Bus
Address bus carries memory addresses from the processor to other components
such as primary storage and input/output devices. The address bus is
unidirectional close unidirectional. Moving or operating in one direction.

Size and Addressing Capability:

• Width: Measured in bits (e.g., 16-bit, 32-bit, 64-bit), the width of the address
bus determines the number of unique memory locations or devices the system
can address. Imagine the number of lanes on an address in a city; a wider
address bus allows for more specific locations.

• Addressing Range: The width directly translates to the addressable memory

space. For example, a 16-bit address bus can address 2^16 (65,536) memory
locations, while a 32-bit bus can address 2^32 (4,294,967,296) locations.
Addressing Schemes:
There are two main addressing schemes used in embedded systems:

• Von Neumann Addressing: In this traditional approach, the address bus

shares the same physical wires as the data bus. The system uses control
signals to indicate whether data or address information is being sent on the
bus. This is simpler to implement but can limit performance.

• Separate Bus Architecture: Here, the address bus has dedicated wires
separate from the data bus. This allows for simultaneous transmission of
address and data information, potentially improving performance.
Control Bus
The control bus is usually a smaller bus and is used to provide control signals to
most parts of a computer system. For example, memory read and write control
signals are carried by the control bus.

Control Signals:
The control bus transmits various critical signals that synchronize and manage
data transfers. Some key examples include:

• Read/Write: This signal indicates whether the CPU intends to read data
from memory/peripherals (Read) or write data to them (Write).
• Address Valid: This signal signifies that a valid memory address or
peripheral device address is present on the address bus.
• Data Valid: This signal indicates that the data on the data bus is ready to be
read or written.
• Transfer Acknowledge: This signal is sent by the memory/peripheral
device after successfully receiving data from the CPU (write operation) or
acknowledging the completion of a read operation.
• Interrupt Request: This signal is sent by a peripheral device to the CPU to
request its attention, often to indicate an event requiring processing (e.g.,
sensor data ready).

Synchronization and Timing:

• The control bus ensures all components involved in a data transfer
operation are in sync. It dictates the timing of various actions, like when
the address is sent, when the data is transferred, and when
acknowledgments are exchanged. This precise timing is crucial for reliable
and error-free communication.
Bus Organization
The bus organization, also known as bus architecture, defines the overall
structure and communication pathways within an embedded system. It
determines how various components like the CPU, memory, and peripherals
interact and exchange data.

1. Von Neumann Bus (Shared Bus):

This traditional approach uses a single set of wires (data bus, address bus, and
control bus) for all communication. Imagine a single-lane highway carrying
cars, trucks, and traffic signals.

Essential Components :
o Data Bus
o Address Bus
o Control Bus
How it Works:
• CPU Initiation: The CPU initiates the data transfer process by placing the
target address on the address bus and sending the appropriate control signal
(read or write) on the control bus.
• Data Transfer: The memory or peripheral device at the specified address
acknowledges the request, and the data transfer occurs on the data bus.
• Synchronization: Control signals ensure data arrives at the correct time and
the receiving device acknowledges successful completion.

Advantages:
• Simplicity: Easy to implement and requires fewer wires, making it cost-
effective for resource-constrained systems.
• Widely Used: A well-understood architecture with established design
principles and readily available components.
Disadvantages:
• Bottleneck Potential: Since only one operation (data transfer or address
transmission) can happen at a time, it creates a bottleneck for performance
in high-speed systems.
• Limited Scalability: Adding more peripherals can strain the shared bus,
potentially impacting performance.

Control Signals in Von Neumann Bus:

• Shared Responsibility: Since data, address, and control information share
the same bus, additional control signals are needed to differentiate between
them. These signals might indicate the start of an address transmission, data
transmission, or the validity of information on the respective buses.

When to Use a Von Neumann Bus:

• Simpler Systems: Well-suited for less complex embedded systems with
moderate data transfer requirements and limited resources.
• Cost-Sensitive Applications: Ideal for applications where cost is a primary
concern, and performance is not a critical factor.
2. Harvard Bus Architecture (Separate Buses):
This approach separates the data bus and address bus, allowing for
simultaneous data transfer and address fetching. Think of it as a highway with
dedicated lanes for cars (data) and addresses (signage).

Essential Components :
o Data Bus
o Address Bus
o Control Bus - While data and address information have their own lanes, a
separate control bus still exists. It carries control signals (read/write, data
valid, etc.) that synchronize the data transfer process.
Advantages:
• Improved Performance: The separation of data and address buses allows
for concurrent operations, leading to faster data transfers compared to the
Von Neumann bus. This is particularly beneficial for high-performance
embedded systems.
• Reduced Bottlenecks: The dedicated lanes eliminate the single-lane
bottleneck issue of the Von Neumann bus.

Disadvantages:
• Increased Complexity: Separating the data and address buses requires more
wires and control logic, making the design slightly more complex and
potentially more expensive.
• Less Common: Compared to the widely used Von Neumann bus, the
Harvard architecture might require more specialized components or design
expertise.
Control Signals in Harvard Bus:
• Simpler Control: Since data and address information travel on separate
buses, the control signals are less complex compared to the Von Neumann
bus. The control bus primarily focuses on synchronizing data transfers and
handling read/write operations.

When to Use a Harvard Bus:

• Performance-Critical Applications: Ideal for embedded systems where
high data transfer rates and fast response times are crucial.
• Systems with High Data Throughput: Well-suited for applications that
process large amounts of data and require efficient data flow.
Multi-Master Bus
Unlike the traditional bus architectures where the CPU reigns supreme, the
multi-master bus introduces a democratic system of communication within an
embedded system. Here, multiple devices, not just the CPU, can act as "bus
masters," requesting control of the bus to communicate with each other
directly.

Essential Components:
• Data Bus, Address Bus, Control Bus: Function the same way as in other
bus architectures.
• Bus Masters: Devices (including the CPU) that can initiate data transfers
by requesting control of the bus.
• Arbitration Logic: Manages bus access requests from multiple masters,
prioritizing requests based on a predefined scheme (e.g., fixed priority,
round-robin).
How it Works:
• Master Requests Access: A bus master (e.g., a DMA controller or a
peripheral device) needs to transfer data and sends a request signal on the
control bus.
• Arbitration: The arbitration logic evaluates the requests from multiple
masters and grants access to the highest priority master according to the
chosen scheme.
• Data Transfer: The winning master gains control of the data bus, places the
address on the address bus, sends the control signal (read/write), and
transfers the data.
• Bus Release: After the transfer, the master relinquishes control, and the
arbitration logic can handle new requests.

Control Signals in Multi-Master Bus:

• More Elaborate Control: The control bus carries signals not only for data
transfer synchronization but also for bus access requests, arbitration results,
and potential error handling during bus conflicts.
Advantages:
• Flexibility and Scalability: Allows for efficient communication between multiple high-
speed peripherals, reducing reliance on the CPU and enabling faster data exchange. This
becomes crucial in systems with complex interactions between various devices.
• Improved Performance: Direct communication between peripherals can offload
communication tasks from the CPU, potentially improving overall system performance.

Disadvantages:
• Increased Complexity: The arbitration logic and additional control signals add
complexity to the design compared to simpler bus architectures.
• Potential Bus Conflicts: Managing multiple access requests requires careful design to
avoid collisions and ensure fair access for all masters.
• Higher Cost: The additional hardware and design considerations can lead to slightly
higher development costs.

When to Use a Multi-Master Bus:

• Complex Systems with High-Speed Peripherals: Ideal for systems with multiple
devices that need to exchange data directly and frequently, reducing traffic through the
CPU.
• Real-Time Applications: Can be beneficial for real-time systems where time-sensitive
data exchange between peripherals is critical.
Bus Protocols
The bus protocol defines the rules and timing for communication on the bus. It
ensures that different components can understand each other and transfer data
reliably. Here are some common bus protocols used in embedded systems:

• Simple Communication Protocol (SPI): A low-cost, low-complexity

protocol for short-distance communication between a single master (usually
the CPU) and multiple slave devices (peripherals).
• I2C (Inter-Integrated Circuit): Another low-cost protocol for
communication between a master and multiple slaves, often used for low-
speed communication with sensors and actuators.
• CAN (Controller Area Network): A high-integrity protocol designed for
reliable communication in harsh environments, commonly used in
automotive applications.
• AMBA (Advanced Microcontroller Bus Architecture): A family of on-chip
bus protocols for communication between different internal components
within a microcontroller or microprocessor.