Synopsys Design Constraints

(SDC)
 Introduction
• “Synopsys Design Constraints” (aka SDC) is used to
describe design requirements for timing, power, and area
and is the most commonly used format by EDA tools
used for synthesis, static timing analysis, and place and
route.
• These were mainly used for specifying design
characteristics that could not be captured in the HDL.
• SDC commands are based on the Tcl language.
Why SDC is Needed?
• STA tool gets the circuit description from the
corresponding design description i.e.
Verilog ,VHDL
• It also takes in library inputs – mostly to know
about technology-dependent characteristics, e.g.,
delay values through specific gates.
• STA tools need information related to the arrival
time and other characteristics of various signals at
the inputs and the time at which various outputs
are required. These inputs are provided through
timing constraints.
The constraints in SDC format can be broadly
categorized as :-

• Constraints for timing

• Constraints for area and power
• Constraints for design rules
• Constraints for interfaces
 Constraints for Timing
• Constraints for timing provide guidance on design
parameters that affect operational frequency. It includes
commands to specify clock characteristics, delays on port,
and pins and paths.

Eg –
create_clock
create_generated_clock
set_clock_groups set_clock_latency
set_clock_transition set_clock_uncertainty
set_clock_sense set_propagated_clock
set_input_delay set_output_delay
Constraints for Area and Power
• Constraints for area and power include commands that
provide guidance on the area a design must fit within and
power requirements for optimization.

set_max_area
create_voltage_area
set_level_shifter_threshold
set_max_dynamic_power
set_level_shifter_strategy
set_max_leakage_power
Constraints for Design Rules
• Constraints for design rules include commands that
provide guidance on some of the requirements of the target
technology.

set_max_capacitance
set_min_capacitance
set_max_transition
set_max_fanout
Constraints for Interfaces
• Constraints for interfaces include commands that provide
guidance on the assumptions design needs to make about
blocks it will be connected to or interacting with in a
subsystem or chip or SoC.

set_drive
set_driving_cell
set_input_transition
set_load
set_fanout_load
set_port_fanout_number
 Creating Clock
The command to define a clock is create_clock

Period – Define period of clock

create_clock -period <arg>
Waveform : The rise and fall edges over one cycle.
create_clock -period 4 –waveform {0 2}
Object : The source the clock comes from. It can be a port
or a pin (for example, a PLL output)
create_clock -period [get_port my_clock_port]
create_clock -period 10-name CLK -waveform {0 2} [get_ports A/N/P]
 Create generated clock
If a primary clock goes through a clock generator such as a
clock divider then the divided clock is said to be a “generated
clock”.

create_generated_clock -source [get_ports clk_1] -divide_by 2 -add -

name CLK2 [get_pins clock_div/Q]
Clock Uncertainty
• clock uncertainty defines a worst-case values about things
we are not certain about regarding the clock.

• The Oscillator/PLL generating the clock doesn’t generate a

clean clock with a constant period. Instead, the generated
clock has an error margin meaning that the clock period
changes over time.
How to Apply Clock Uncertainty
• During Synthesis we don’t have a clock tree so we need to
assume a clock skew. Some designers assume 20% of the
clock period but this value can change depending on the
project.

set_clock_uncertainty [expr $pll_jitter + $clock_period*0.20] [get_clocks

myClk]
After CTS there is a clock tree and we know the cell delays
but we don’t have clock routes yet1 . We can relax the
clock uncertainty and leave a term to account for the
routes.

set_clock_uncertainty [expr $pll_jitter + $clock_period*0.10]

[get_clocks myClk]
 but we still have 2 sources of uncertainties: The PLL jitter
and the network jitter

set_clock_uncertainty [expr $pll_jitter + $clock_period*0.03] [get_clocks

myClk]
Input and Output Delay

• The current block communicates with other blocks through

the I/O ports.
• To fully run STA on the block we need to inform the tool
about the delays in the other blocks so that when we
integrate the blocks we don’t get surprises and we meet
timing
The delay coming from input ports is called input delay
• 𝑇𝑐𝑞 of the launching FF
• Combinational path delay in the launching block.
• Net delay between the two blocks.

set_input_delay 6.5 -clock CLK1 -network_latency_included [all_inputs]

The delay coming from output ports is called output delay
• 𝑇𝑠𝑒𝑡𝑢𝑝 of the capturing FF
OUTPUT DELAY
• Combinational path delay in the capturing block.
• Net delay between the two blocks.

set_output_delay 4 -clock CLK1 -network_latency_included [all_inputs]

 Conclusion
Summary:
• SDC commands are critical for defining the
timing and design constraints.
• Proper usage ensures that the design meets
its performance and functional requirements.
Call to Action:
• Explore more SDC commands and their
applications in tools.
• Practice creating and applying constraints in
design projects.
THANK YOU
 Basic Concepts of SDC
• Key Concepts:
• Timing Constraints: Define clock
characteristics and timing requirements.
• Environment Constraints: Specify the
operating conditions and design environment.
• Design Rules: Set up rules for design
implementation.
• Ensures design correctness and robustness.