Low Power Design

Techniques and Power

Dissipation
Management
Low power design is crucial in modern VLSI circuits, where
power dissipation is a major concern. This presentation
explores techniques for reducing power consumption in digital
circuits.
• Definition of Low Power Design
• Design approach aimed at minimizing power consumption in electronic devices.
• Critical for extending battery life, reducing heat dissipation, and enhancing overall
efficiency.

• Importance of Low Power Design

• Prolongs battery life in portable devices (smartphones, wearables, IoT devices).
• Reduces operational costs (lower power consumption translates to lower electricity
bills).
• Minimizes heat generation, improving reliability and longevity of components.

• Challenges in Low Power Design

• Balancing performance with power efficiency.
• Meeting stringent power budgets without sacrificing functionality.
• Addressing leakage currents and standby power consumption.

• Key Techniques and Strategies

• Architectural Optimization:
o Use of low-power modes.
o Power gating: shutting off power to unused blocks or peripherals.

• Technology Selection:
o Choosing low-power components (low leakage transistors, energy-efficient
microcontrollers).

• Clock Gating and Dynamic Voltage and Frequency Scaling (DVFS):

o Adjusting clock speeds and voltages dynamically based on workload.
Types of Power Dissipation
Static Power Dissipation
Leakage currents occur even
when the circuit is idle, due to
sub-threshold conduction and
gate leakage.
Dynamic Power Dissipation
Switching activity, caused by
changes in logic states, leads to
dynamic power dissipation,
which is proportional to the
switching frequency and load
capacitance.
Short-Circuit Power Dissipation
Short-circuit power dissipation
occurs during the brief period
when both PMOS and NMOS
transistors are simultaneously
conducting, resulting in a direct
path for current flow.
Reducing Dynamic Power

Clock Gating
1
Disabling the clock signal to idle modules prevents unnecessary switching activity, reducing
dynamic power consumption.

Dynamic Voltage and Frequency Scaling (DVFS)

2
Adjusting the voltage and frequency according to workload requirements reduces both dynamic
and static power by lowering the voltage and frequency during periods of low activity.

Multi-VDD Designs
3
Using different supply voltages for different parts of the circuit based on performance
requirements balances power and performance.

Clock Tree Optimization

4
Optimizing the clock distribution network reduces clock-related power consumption by
minimizing clock skew and reducing the number of buffers and inverters.
Reducing Static Power

Power Gating High Threshold Voltage

(High-Vth) Transistors
Completely shutting off
power to idle blocks
Using transistors with a
eliminates leakage
higher threshold voltage
power in inactive
reduces sub-threshold
regions. Sleep
leakage currents. This
transistors disconnect
can slightly slow down
the power supply from
switching speeds.
the idle block.

Multi-Threshold CMOS Substrate Biasing (Body

(MTCMOS) Biasing)

Combining high-Vth Adjusting the substrate

and low-Vth transistors (body) bias voltage
balances speed and modulates the threshold
leakage reduction. voltage, reducing
High-Vth is used for leakage. Techniques
non-critical paths, low- include forward body
Vth for critical paths. bias (FBB) or reverse
body bias (RBB).
Reducing Static Power (Continued)

Leakage Control Transistors Dynamic Voltage Scaling (DVS)

Inserting additional
transistors to control
Dynamically adjusting supply
leakage paths blocks
voltage based on performance
leakage current paths
needs lowers supply voltage and
when the circuit is idle.
reduces leakage power.

Gate Oxide Thickness Low Leakage Libraries

Using thicker gate oxides for Using standard cell libraries

transistors reduces gate oxide
leakage currents. This can
increase gate capacitance,
slowing down transistor
switching.
designed for low leakage
optimizes cells for reduced leakage
currents.
Reducing Short-Circuit Power
Minimizing Voltage
Transitions
Reducing Load Capacitance
Proper sizing of
transistors ensures faster
transitions and reduces
the overlap period of
PMOS and NMOS
transistors being on
simultaneously.
Minimizing the
capacitive load driven
by each gate reduces the
time for which short-
circuit currents can
flow.
Implementing Multi-
Threshold CMOS
(MTCMOS)
Using high-threshold
voltage transistors for
gates that are not
timing-critical reduces
leakage and short-
circuit currents.

1 2 3 4 5 6

Optimizing Gate Drive Supply Voltage Scaling Designing for Balanced

Strength
Adjusting the drive
strength of gates
balances performance
and power consumption,
minimizing unnecessary
short-circuit currents.
Lower supply voltages
reduce the peak short-
circuit current, as short-
circuit power is
proportional to the
square of the supply
voltage.
Rise/Fall Times
Ensuring that the rise
and fall times of signals
are balanced minimizes
the period during which
both PMOS and NMOS
transistors conduct
simultaneously.
Power Management Techniques
Power Domains
Partitioning the chip into
multiple power domains
allows for independent
control of power to different
areas, enabling selective
shutdown of inactive
regions.
Adaptive Voltage Scaling (AVS)
Dynamically adjusting the
supply voltage in real-time
based on performance
requirements reduces power
consumption by operating at
the minimum voltage
necessary for the required
performance level.
Voltage Islands
Separating regions within a
chip operating at different
voltage levels optimizes
power consumption by
providing higher voltages to
performance-critical regions
and lower voltages to non-
critical regions.
Dynamic Frequency Scaling (DFS)
Adjusting the clock
frequency dynamically
according to the workload
reduces power consumption
by lowering the frequency
during periods of low
activity.
Power Management Techniques
(Continued)
Clock Gating
Disabling the clock signal to
idle parts of the circuit
prevents unnecessary
switching activity, reducing
both dynamic and static
power consumption.
Dynamic Power
Management (DPM)
Implementing power
management policies that
dynamically adjust power
states based on activity
optimizes power usage by
transitioning between
different power states such
as active, idle, and sleep
modes.
Power Gating
Completely shutting off
power to idle blocks using
sleep transistors eliminates
both static and dynamic
power consumption in
inactive regions.
Thermal Management
Monitoring and managing
the chip’s temperature to
prevent overheating ensures
reliable operation and can
indirectly reduce power
consumption by adjusting
performance to maintain
thermal limits.
Low Power Design Flow
Power Intent Specification
1
Specifying power management strategies using Unified Power Format (UPF) or Common
Power Format (CPF) provides a standardized way to define and implement power management
techniques during design and verification.

Power-Aware Synthesis
2
Optimizing the design for low power during synthesis ensures that power considerations are
incorporated into the logic implementation.

Power-Aware Place and Route

3
Placing and routing components with power consumption in mind minimizes power dissipation
and ensures efficient power distribution.

Power Analysis and Optimization

4
Analyzing the power consumption of the design and identifying areas for improvement allows
for further optimization and reduction of power dissipation.