ARM BASED SoC PHYSICAL

DESIGN

INTERNAL GUIDE BY:

DR.JAYARAJ U KIDAV Kushagra singh
Scientist/Engineer ‘E’ UCC21ECES08
NIELIT CALICUT MTECH ES 2021-
23

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 CONTENTS
• Background/introduction
• Related works
• Problem statement
• Research Proposal/Contribution
• Project Objective
• Methodologies
• Tools Required
• Expected Outcomes
• Gantt Chart
• References

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 BACKGROUND /INTRODUCTION
• In the current post-PC era shaped by smartphones, tablets, wearables and cyber-physical systems, the primary
metrics of silicon chips have changed from clock-frequency to cost, form-factor, and power consumption.
On-chip integration of functional hardware is now more important than ever[7]
• A System-on-Chip (SoC) is an integrated circuit that packages most of the necessary computing components
into a single chip. These include: (1) a system master, such as a CPU or DMA controller; (2) system
peripherals, such as memory blocks, timers and external digital/analog interfaces; and (3) a system bus that
connects master and peripherals together using a specific bus protocol[1]
• Use of open-source tools for physical designing of Arm based SoC

[7] R. Serrano et al., "A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications," 2021 18th International SoC Design Conference (ISOCC), 2021, pp.
375-376, doi: 10.1109/ISOCC53507.2021.9613880
[1]https://armkeil.blob.core.windows.net/developer/Files/downloads/research/Research%20Enablement%20Kits/SoC%20Whitepaper.pdf
.
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 RELATED WORKS
Sl.No Citation
1 J. Lee et al., "An Energy-efficient
Floating-Point DNN Processor using
Heterogeneous Computing
Architecture with Exponent-
Computing-in-Memory," 2021 IEEE
Hot Chips 33 Symposium (HCS),
2021, pp. 1-20, doi:
10.1109/HCS52781.2021.9566881
2 Arm, “AMBA 3 apb protocol v1.0
specification.”
3 Arm, “Amba 3 ahb-lite protocol v1.0
specification.”
Key Idea
Use of Floating point number
system for power efficient
heterogeneous system
development
Specification of AMBA APB Bus
Specification of AMBA AHB Bus
Approach Remark
1) Heterogeneous FP Computing Arch. Floating point
: Separate optimization of FP number can be used
computing: Realize 2 cycles FP MAC to enhance
w/ CIM (2) Exponent Computing-in- performance of
Memory: In-memory AND/NOR + BL system
charge reusing: Total memory power
46.4% 2) Mantissa Free Exponent
Calculation: Removing redundant
normalization: Total MAC power
14.4%
Working of Amba APB Bus and Use of AMBA APB
connection of peripherals BUS
Working of Amba AHB Bus and Use of AMBA AHB
connection of peripherals BUS
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 RELATED WORKS
Sl.No Citation Key Idea Approach Remark

4 T. N. Tan, P. Duong-Ngoc, T. X. Pham Use of AMBA AXI in SOC design Comparing AXI with AHB AXI protocol is faster than
and H. Lee, "Novel Performance AND APB protocols APB,AHB
Evaluation Approach of AMBA AXI-
Based SoC Design," 2021 18th
International SoC Design
Conference (ISOCC), 2021, pp. 403-
404, doi:
10.1109/ISOCC53507.2021.9613920
.
5 P. Bodmann, G. Papadimitriou, D. Porting of os in Soc based systems Use of os for multitasking OS use make SoC task
Gizopoulos and P. Rech, "The Impact and efficiency of task faster
of SoC Integration and OS
Deployment on the Reliability of
Arm Processors," 2021 IEEE
International Symposium on
Performance Analysis of Systems
and Software (ISPASS), 2021, pp.
223-225, doi:
10.1109/ISPASS51385.2021.00040.

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 PROBLEM STATEMENT
• To develop ARM based SoC system with Use of Cortex M0 core and AHB,APB,AXI BUS protocol to
integrate other subsystems like clock ,AES Block, FPU Block and Physical design of SoC using open
source tools

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 RESEARCH
PROPOSAL/CONTRIBUTION
• Adding multiple IP Cores and OS support and behavior of the system [6]
• The implementation of errors Block as exceptions to the CPU can be explored
• Use of floating-point Number for energy Saving[2]
• Make better GDS –ll design for better performance

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 PROJECT OBJECTIVE
• Developing ARM Based SoC system that can Perform instructions Using ARM ISA and implement
it on FPGA [8]
• Physical design of ARM Based SOC system

[8]https://developer.arm.com/documentation/dui0662/b/The-Cortex-M0--Instruction-Set/Instruction-set-summary 8
 METHODOLOGY
• To Understand use of ARM STANDARD ISA [5]
• VERILOG for coding of IP core Development
• Addition of error block to check error
• AXI Interface to connect Sram ,Dram, Main microcontroller
• GDS –II layout through open source tools
• AHB & APB interface to connect clock,GPIO,UART [4][3]

[4] Arm, “AMBA 3 apb protocol v1.0 specification.” http://web.eecs.umich.edu/~prabal/teaching/eecs373-f12/readings/ARM_AMBA3_APB.pdf.

[5] Arm Developer, “CMSIS cortex microcontroller software interface standard.” https://developer.arm.com/embedded/cmsis.
[6]P. Bodmann, G. Papadimitriou, D. Gizopoulos and P. Rech, "The Impact of SoC Integration and OS Deployment on the Reliability of Arm
Processors," 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2021, pp. 223-225, doi:
10.1109/ISPASS51385.2021.00040
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 TOOLS/RESOURCES REQUIRED
• HARDWARE
ARTY A7 100T FPGA
• SOFTWARE
XILINX Vivado®
Graywolf
Qrouter
ARM Cortex M0+ core IP
USART,I2C Ips
FPU IP

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 EXPECTED OUTCOMES
• Full functioning ARM Based SoC system
• RTL To GDS –II implementation
• Better functionality of ARM ISA
• Addition of error block
• Use of Floating point number[2]

[2] J. Lee et al., "An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory," 2021
IEEE Hot Chips 33 Symposium (HCS), 2021, pp. 1-20, doi: 10.1109/HCS52781.2021.9566881
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GANTT CHART

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 REFERENCES
[1]https://armkeil.blob.core.windows.net/developer/Files/downloads/research/Research%20Enablement
%20Kits/SoC%20Whitepaper.pdf
[2] J. Lee et al., "An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing
Architecture with Exponent-Computing-in-Memory," 2021 IEEE Hot Chips 33 Symposium (HCS), 2021, pp. 1-20,
doi: 10.1109/HCS52781.2021.9566881
[3] Arm, “Amba 3 ahb-lite protocol v1.0 specification.”
http://www.eecs.umich.edu/courses/eecs373/readings/ARM_IHI0033A_AMBA_AHB-Lite_SPEC.pdf.
[4] Arm, “AMBA 3 apb protocol v1.0 specification.” http://web.eecs.umich.edu/~prabal/teaching/
eecs373-f12/readings/ARM_AMBA3_APB.pdf.
[5] Arm Developer, “CMSIS cortex microcontroller software interface standard.”
https://developer.arm.com/embedded/cmsis.
[6] P. Bodmann, G. Papadimitriou, D. Gizopoulos and P. Rech, "The Impact of SoC Integration and OS
Deployment on the Reliability of Arm Processors," 2021 IEEE International Symposium on Performance Analysis
of Systems and Software (ISPASS), 2021, pp. 223-225, doi: 10.1109/ISPASS51385.2021.00040.

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 REFERENCES
[7] R. Serrano et al., "A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications,"
2021 18th International SoC Design Conference (ISOCC), 2021, pp. 375-376, doi:
10.1109/ISOCC53507.2021.9613880.
[8] https://developer.arm.com/documentation/dui0662/b/The-Cortex-M0--Instruction-Set/
Instruction-set-summary

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