COMPOUND CONFIGURATION

MULTISTAGE AMPLIFIER

Cascaded Connection
Output of one stage is connected to the input of another
stage.

Amplifier 1 Amplifier 2

Vin 1 Gain = AV1 Vo 1 Gain = AV2 Vo 2

Overall gain AV = VO2 / Vin 1 = Av1  AV2

MULTISTAGE AMPLIFIER
Cascaded BJT Amplifier
297 VCC

VCC
RC2
RC1 V1o R3 V2o
R1 Q2
C2
Q1 R4
Vi C1 RE2
R2 Cs2

RE1 Cs1

V1o RC1 || RL1 V2 o RC 2 || RL 2

Gain AV1 =   Gain AV2 = 
V1 re V1o re
 VCC
VCC

RC1 RC2
R C1 || R 3 R
||R R 4 || β 2 * re2
V1O
V2O

A v1R  
AQv2  R  re1|| R Q
C2 3
1
2

C1
R2 A v2 
C C2

1
L 2
re2R
R4
R
re2
Vi E2
E1
Cs1 Cs2

RC2
RC1 Ic1 R3 V2O
R1 V1O Ib2 c
b Ib1 2Ib2
c 1Ib1 RL
Overall
R
Vi
gain,
r 2
A v  A * A v2i1
R4 ri2
v1
e
e
Input Impedance, Zi  R 1 * R 2 * β1 * re1

Output Impedance, Zo  R c2 || ro

RC2
RC1 Ic1 R3 V2O
R1 V1O Ib2 c
b Ib1 2Ib2
c 1Ib1 RL
R4 ri2
R2 ri1
Vi e
e
 +20V 20V

2.2K 1.5K
V1O V2O
15K 22K

Q1 Q2
10µf
4.7K C2 6.8K
Vi 1K 1K
20µf 20µf

Draw the (i) Input and (ii) output voltage waveshape for
different values of Vi (a) 25µV (b) 1mV (c) X mV, where X is
last two digits of your Roll No.
 Cascaded FET Amplifier
V DD
504
RD1 Ic1
RD1 D V1O
G
gmVgs
Q1 RG1
Vi Vi
Ci S
RG1
Rs1
Cs1

AV1 = -gm1RD1
 Cascaded FET Amplifier
504
VDD

VDD
RD2
RD1
Vo2
Q2
Vo1
C2
Q1
Vi RG2
Ci
RG1 Rs2
Cs2
Rs1
Cs1
 Cascaded FET Amplifier
504

AV2 = -gm2RD2
RD1
D V1O
RD2
G D V1O
gmVgs G
gmVgs
RG1
Vi S RG2
Vi S

Overall
AV1 =gain
Input V1 AOutput
-gm1RAImpedance
V2 = (-gImpedance
ZinR=
m1 D1)(-g
RG1m2RD2
ZO) = RD2
D1
 Cascaded FET Amplifier
504
VDD

VDD
AV2 = -gm2RD2 RD2
AV1 = -gm1RD1
RD1
Vo2
Q2
Vo1
C2
Q1
Vi RG2
Ci
RG1 Rs2
Cs2
Rs1
Cs1

Overall gain V1A

InputAImpedance
Output
V2 = (-gImpedance
ZinR=
m1 D1)(-g
RG1m2RD2
ZO) = RD2
BJT COMPOUND
CONFIGURATIONS
CASCODE CONFIGURATION
CASCODE CONFIGURATION
 CASCODE CONFIGURATION

This is a CE – CB
This arrangement provides high input combination.
impedance but a low voltage gain.

The low voltage gain

reduces the Miller Input
Capacitance therefore
this combination
works well in high
frequency applications.
CASCODE CONFIGURATION
CASCODE CONFIGURATION

Consider the cascode amplifier above

a) Find the voltage gain Av = vo/vi
b) Find the input resistance Ri
c) Find the output resistance Ro
 Darlington Connection
299
Two transistors are connected in
such a way that emitter current of
one is fed to the base of another, so
that the overall current gain is the
product of their individual current Q1
gains. IB1
Q2
It is also known as superbeta IE1
transistor IE1 = (1+ 1 )  IB1 IE2
IE2 = (1+ 2 )  IB2
IE2 = (1+ 2 )  (1+ 1 )  IB1
Overall  = 1 2
IE2  2  1  IB1
2N999 npn darlington transistor
VBE = 1.8V at IC = 100mA
βD = 4000 at IC = 10mA
βD = 7000 at IC = 100mA
Maximum βD = 70,000 at IC = 100mA
 DC bias of Darlington Circuit

VCC  VBE VCC

IB 
RB   D RE IC
RB

I E   D  1I B   D I B IB
D

VBE IE
VE  I E RE
RE

VB  VE  VBE
 DC bias of Darlington Circuit
18  1.6
IB   2.56 A 18V
3.3M  8000 * 390R
IC
3.3M

I E  8000 * 2.56μ.  20.48mA IB

D

VE  20.48mA * 390R  8V IE
VBE
VBE = 1.6V 390R
VB  8  1.6  9.6V βD =8000
 AC analysis of Darlington Circuit
VCC

Ii Ib
IC
DIb
RB Vi
Vi
RB ri
Ci Ib

VO
RE
D = 8000
Ci VO
VBE = 1.6V
IE
RE
 AC Input Impedance of Darlington Circuit

Ii Ib Vi  Vo
DIb Ib 
Vi ri
RB ri
Vo  I b   D I b RE
VO
RE
βD =8000
ri = 5K Vi  I b ri  1   D RE   I b ri   D RE 

Vi
Z i   RB || ri   D RE 
Ii
 AC Current Gain of Darlington Circuit

Io
Ii Ib Ai 
DI b Ii
Vi
RB ri Io  Ib   D Ib   D Ib
Vi  I b ri   D RE 
VO

Io
RE RB
Ib  Ii
ri   D RE   RB
Io Io Ib RB
Ai    D RB
Ii Ib Ii RB   D RE I b  Ii
 D RE  RB
Vi
Z i   RB || ri   D RE 
Ii
 AC Output Impedance of Darlington Circuit
ri VO
Vo
Ib ZO
Zo 
VS
RE RL Io
RB
DI b
Vo Vo
Io     D Ib
ri IO RE ri
Vo Vo  Vo 
RE VO Io     D   
DIb RE ri  ri 
Vo 1
Zo  
Io 1 1 D
 
RE ri ri
 AC Voltage gain of Darlington Circuit

ri Vo
AV 
Ib Vi
VS
RE VO
DIb Vo  I b   D I b RE
Vo  RE   D RE I b
Vi  I b ri  Vo Vi  I b ri  RE   D RE 
Vi
Vo  RE   D RE 
ri  RE   D RE 
AV 
Vo

RE   D RE 
1
Vi ri  RE   D RE 
Summery of Darlington connection
•Super beta transistor, D = 1  2.
•High current gain, can amplify very small signal.
•Increased input impedance.
•Reduced output impedance.
•Unity voltage gain.
CMOS
CMOS Circuit
594
CMOS Circuit
594
CMOS Circuit
594
CMOS Circuit
594
 CMOS Circuit
594

Complementary Metal Oxide

Semiconductor Field Effect Transistor
VDD = 5V VDD = 5V
VGS = -5V S VGS = 0V S
pMOS pMOS
G G

D VV D
o =
o 5V Vo = 0V

D D
Vi =V0V
i Vi = 5V
G nMOS G nMOS

CMOS is used
S as S

an inverter
V = 0V
GS VGS = 5V
CMOS Circuit
594
 Current source

VDD =10V
= 24V
IL = 10A
IL = 8 mA
RL = 2
1
IDSS= 8 mA RRLL=1K
= 5K
2K
IS = 10A VP = - 5 V VO = ?

2
 VGS 
I D  I DSS 1  
 VP 
 BJT Current source
310

VCC
R1
VB   VEE 
RL
R1  R2
IC

VB VE  VB  0.7
R1 VE  (VEE )
R2 IE RE IE   IC
RE

-VEE
 BJT - Zener Current source
310

VCC

RL
VZ  VBE
IC IE   IC
VB
RE
R1
VZ RE
IE

-VEE
Current Mirror Circuit IE IE
307
IB  
VCC
V 1  
IX RX
IL RL IC  I E
IC 2IB
IC
I X  IC  2I B
Q1 Q2 2I E
IB IB I X  IE 
IE V1 IE 
IL1 RL1
  2
I
I X  
X  I
 
 I E  I E
L