Implementation of Ladner

Fischer Adder(16 bit)

Design : RTL to GDSII Flow
Presented By:
Rashi Pandey
(Mtech Microelectronics, BITS Pilani ,Goa Campus) Intel, SoC designer
 Introduction
• Achieving minimum computation time and reduced power utilization is of great interest in
VLSI Design. This paper presents the designing of an approximate adder such as Ladner
Fischer with the use of parallel computing.
• Earlier technologies have used the redundant method of Ripple Carry Adders to perform
arithmetic operations, but multipliers are an important part of any operational unit which
uses large adders in the multiple sequences and the execution rates should be minimized.
• The topology implemented in this paper is developed using VHDL, and the functionality
is verified using simulation tools such as Genus, Innovus, NC Launch, etc. from Cadence
and synthesized to 90 nm CMOS Technology. For 16-bit addition, the current design
dynamic power obtained is 0.0187 W and the total area cell covered is 26%.
 Comparative Topology

4 Bit Carry Ahead Adder 16 Bit Ladner Fischer

Tree
 Stages In Tree Adders
• The parallel prefix adder consists of sum generated using the prefixes obtained in the
intermediate stages and the inputs.
• The sum is formed from three stages namely, Precomputation, Prefix, and Post
Computation. Precomputation involves intermediate carry signals that generate and
propagate pairs A carry is generated where a group generates the upper (more
significant) or the lower portion, and the upper portion propagates that carry using
AND, XOR gates.
• The carry propagation occurs when either of the signals attains 1 bit as shown in Equ.
(1). Pi = Ai XOR Bi (1) The carry generation only occurs when both input values are
logical level 1 as shown in Equ.(2). Gi = Ai . Bi.
 Stages In Tree Adders
• The prefix stage involves computing propagate/generate signals at each
stage of the three adder by using black and gray cells. The black cells
group generates bits and gray cells containing only the group generate
logic which is used at the final cell position in each column.
• P[i, i + 1] = P[i] · P[i + 1] ; G = (G[i] · P[i + 1]) + G[i + 1]
 Stages In Tree Adders
• At last, post computation involves the carry and sum bit formation for
each bit operand. Carry is grouped from all the bits and reaches the end
using one last adder. Where P is the propagate signal and C is the last
carry obtained from the architecture which is explained in
• S[i + 1] = P[i + 1] C[i]
 ASIC Flow
• At the industry level, the procedure from converting a module in VHDL to
synthesis level and further to gate-level representation as cells in the
layout is called as Physical Design or ASIC flow or RTL TO GDS II since
the transistor level description is converted into layout format information
in GDS II file.
• The following description is for flow in 90 nm CMOS technology. Tools
used are Cadence NC Launch for simulation and GENUS for synthesis
and physical layout using INNOVUS
 Simulation using NC Launch and synthesis
using Genus
• For carrying out the functional simulation, NC Launch is used to compile
and elaborate the Verilog codes and waveforms . The synthesis was
performed using Genus to obtain the RTL level. The circuit is logically
implemented using the synthesis such as standard library cells that are
substituted in the circuit from EDA Tool
 Simulation with synthesis delay
• After the synthesis is performed using GENUS, the netlist is generated,
and constraints are ready in .sdc file. Hence, the delays are expected to be
found in the post-synthesis simulation for timing.
 Genus generated reports
• Genus generated files are formed in the same library such that these
contain the reports of the schematic implemented and these helps to build
the perspective about the Area, Timing, Power consumption, and Gates.

Power Report
Timing Report

Area Report
 Physical Layout
• The final output of a frontend design or circuit design or logic design is a
netlist. The netlist contains the logical functionality of a chip. This netlist
could be viewed as a plethora of instances with interconnections (nets)
between them based on the functionality to implement. This connectivity
information in a netlist is a layer of abstraction of the hardware which
must be converted to a physically realizable format (having geometric
shapes) that is manufacturable. The Innovus tool is to carry out physical
design and finally generating a GDSII file.
 Design Steps
• The designing steps are as followed, the first step is to import design and
library files as required, the second step is to build layout area (Floor plan,
dimensions), the third step is to place the standard cells from the design
(percent core utilization is visible) and the final step is to route the nano
route and checks for the DRC errors using the Innovus. The Innovus
generates the netlist, .sdf file, GDSII files. The simulation is for the post-
layout of the design
Physical layout with pins
Upgraded layout
 Future Scope
• For future research, a new type of PPA adders such as Kogge Stone and
so on can be examined to implement the change in the Verilog modules.
Further, different tree multipliers such as Vedic Multipliers, Logarithmic
Multipliers, and so on can be used with the above adders multiple times.
And also for ease of use in designing the Multiplier Accumulator (MAC)
unit where the arithmetic operations are delaying the results using the
above-stated multipliers and adders.
Thank You!!
Any Questions??