Optimizing Power @ Standby

Memory

Benton H. Calhoun
Jan M. Rabaey

Low Power Design Essentials ©2008 Chapter 9

 Chapter Outline

 Memory in Standby
 Voltage Scaling
 Body Biasing
 Periphery

Low Power Design Essentials ©2008 9

 Memory Dominates Processor Area

 SRAM is a major source of static power in ICs,

especially for low power applications
 Special memory requirement: need to retain state
in standby
 Metrics for standby:
– 1. Leakage power
– 2. Energy overhead for entering/leaving standby
– 3. Timing/area overhead
BL BL
WL

Q
M3 M6
M2 M5
M1 M4
QB

Low Power Design Essentials ©2008 9

 Reminder of “Design Time” Leakage Reduction

 Design-time techniques (Ch 7) also impact

leakage
– High VTH transistors
– Different precharge voltages
– Floating BLs
 This Chapter: adaptive methods that
uniquely address memory standby power

Low Power Design Essentials ©2008 9

 The Voltage Knobs

NMOS VDD - VDD

 Changing internal (DIBL)

0 0 0 -

0 C
1
0
voltages has different

Leakage reduction (ratio)

B1
impact on leakage of 10-1 VTH  k (   2  2 )

various transistors in VTH  

B2
VDD
cell 10-2 0
A2 VDD
 Voltage changes - 0
+

accomplished by 10-3
A1 VDD 0

playing tricks with 0 0

L = 90 nm, tOX = 2 nm
VDD = 1 V
peripheral circuits 10-4
+
S = 100 mV/decade
K = 0.2 V1/2, 2 = 0.6 V
 = 0.05

10-5
0 0.2 0.4 0.6 0.8 1.0
Offset voltage,  (V)

Low Power Design Essentials ©2008 [Ref: Y. Nakagome, IBM’03] 9

 Lower VDD in Standby
Active mode
VDDH
VDD VDDlow
VDD VDDL
Standby mode drowsy drowsy

VDD_SRAM

Example
SRAM

 Basic Idea: Lower VDD lowers leakage

– sub-threshold leakage
– GIDL
– gate tunneling
 Question: What sets the lower limit?

Low Power Design Essentials ©2008 [Ref: K. Flautner, ISCA ’02] 9

 Limits to VDD Scaling: DRV

Data Retention Voltage (DRV):

Voltage below which a bitcell loses its data
0.4
130 nm CMOS
V =0.4V
0.3 DD

(V)
2 0.2 V =0.18V
DD
V

That is, the supply voltage at 0.1 VTC

1
which the Static Noise Margin VTC
2
(SNM) of the SRAM cell in
standby mode reduces to zero. 0
0 0.1 0.2 0.3 0.4
V (V)
1
Low Power Design Essentials ©2008 [Ref: H. Qin, ISQED ’04] 9
 Power savings of DRV

1.4 mm

60

Leakage Current (μA)

50

40

IP 30 Measured
Module DRV range
1.4 mm of 4kB 20
SRAM
10

0
0 0.2 0.4 0.6 0.8 1
Supply Voltage (V)

• More than 90% reduction in

Test chip in 130 nm CMOS leakage power with 350mV
technology with built-in voltage standby VDD (100mV guard
regulator band).

Low Power Design Essentials ©2008 [Ref: H. Qin, ISQED’04] 9

 DRV and Transistor Sizes

190

180
DRV (mV)

170

160 Ma
Mp
150 Mn
Model
140
0 1 2 3
Width Scaling Factor

With Ma, Mp and Mn the access transistor, PMOS pull-up

and NMOS pull-down, respectively

Low Power Design Essentials ©2008 [Ref: H. Qin, Jolpe ’06] 9

 Impact of Process “Balance”

Stronger PMOS or NMOS (SP,SN) in sub-

threshold lowers SNM even for typical cell
Low Power Design Essentials ©2008 [Ref: J. Ryan, GLSVLSI’07] 9.
 Impact of Process Variations on DRV

 DRV varies widely from cell to

cell
 Most variations random with
some systematic effects (e.g.
module boundaries)
 DRV histogram has long tail

DRV histogram for 32 kBit SRAM

6000

5000 130 nm CMOS

4000

DRV Spatial Distribution 3000

2000

1000

0
100 200 300 400
DRV (mV)
Low Power Design Essentials ©2008 [Ref: H. Qin, ISQED’04] 9.
 Impact of Process Variations on DRV

DRV distribution for 90 nm and 45 nm CMOS

0.10
© IEEE 2007

0.08
Frequency

0.06

0.04

0.02 90 nm tail 45 nm tail

0
50 100 150 200 250 300 350

DRV (mV)
Other sources of variation:
Global variations, data values, temperature (weak), bit-line voltage (weak )

Low Power Design Essentials ©2008 [Ref: J. Wang, CICC’07] 9.

 DRV Statistics for an Entire Memory

 DRV distribution is neither normal nor lognormal

 CDF model of DRV distribution (FDRV(x) = 1- P(SNM < 0, VDD=x))
2
  k(x  V )  1    k(x  V ) 
FDRV (x)  1 erfc  0 0
 
erfc  0

0


 2 0  4   2 0 

350

Model
Normal
300 LogNormal
Worst DRV (mV)

Monte-Carlo

250

200

150
© IEEE 2007
100
3 4 5 6 7 8
Memory size s

Low Power Design Essentials ©2008 [Ref: J. Wang, ESSCIRC 2007] 9.

 Reducing the DRV
6000

5000

4000

3000

2000

1000

0
100 200 300 400

DRV (mV)
Chip DRV

1. Cell optimization
2. ECC (Error Correcting Codes)
3. Cell optimization + ECC
Low Power Design Essentials ©2008 9.
 Lowering the DRV Using ECC

Data In
ECC Write
Encoder

D P

Data Correction
Data P

SRAM with ECC

ECC
Read Data Out
Decoder
- 15 -
Error Correction Challenges
 Hamming [31, 26, 3] achieves 33%
 Maximize correction rate
power saving
 Minimize timing overhead  Reed-Muller [256, 219, 8] achieves
 Minimize area overhead 35% power saving

Low Power Design Essentials ©2008 [Ref: A. Kumar, ISCAS’07] 9.

1K words DRV histogram
Combining Cell Optimization and ECC

300
Original SRAM A

Normalized SRAM leakage current

1
200
Standard Optimized SRAM w/ ECC

100
0.8 50X

0
100 150 200 250 300 350 400 450 500 550 0.6
650mV
Original DRV (mV)

B
0.4
1K words DRV histogram

300 320mV
Optimized 255mV
200 0.2
C
100
0 D
0 0.2 0.4 0.6 0.8 1
0
100 150 200 250 300 350 400 450 500 550 VDD (V)
Optimized DRV (mV)

SRAM Standby VDD

1K words DRV histogram

300
Optimized+ECC A Standard 1V
200
B Standard DRVMAX+100mV
100
C Optimized DRVMAX+100mV
0
100 150 200 250 300 350 400 450 500 550 Optimized DRVECC_MAX+100mV
D
- 16 -
Optimized DRV with Error Correction (mV) with ECC

Low Power Design Essentials ©2008 [Ref: A. Kumar, ISCAS’07] 9.

 How to Approach the DRV Safely?

Adjustable VDD
Power
Supply

VCTRL
voltages
“1” “0”
“1” “0”
Reset

Sub-VT Failure Detectors Core Cells

Controller

Using “canary cells” to set the standby voltage

in closed-loop

Low Power Design Essentials ©2008 [Ref: J. Wang, CICC’07] 9.

 How to Approach the DRV Safely?
Less Failure More
power Threshold reliable Canary Replica &
test circuit
Histogram

Multiple sets of
canary cells
SRAM cell

128Kb SRAM
ARRAY
© IEEE 2007 DRV
Mean DRV of Canary Cells (V)

0.8

0.6

0.4

0.2
0.6% area overhead
0
in 90nm test chip
0 0.2 0.4 0.6 0.8
VCTRL(V)
Low Power Design Essentials ©2008 [Ref: J. Wang , CICC’07] 9.
 Raising VSS

 Raise bitcell VSS in standby (e.g. 0 to 0.5V)

 Lower BL voltage in standby (e.g. 1.5V to 1V)

‘0’ is 0.5V 1.0V WL=0V 1.0V

Lower voltage  less 1.5V

gate leakage and GIDL
‘0’ ‘1’
Lower VDS  less sub-
VTH leakage (DIBL)
0.5V
Negative VBS  reduces
sub-VTH leakage

Low Power Design Essentials ©2008 [Ref: K. Osada, JSSC’03] 9.

 Body Biasing
 Reverse Body Bias (RBB) for leakage reduction
– Move FET source (as in raised VSS)
– Move FET body
 Example: Whenever WL is low, apply RBB

Active Standby
VPB VDD
WL
BL WL BLB 0V

VDD
VDD
VDD,VSS
0V

2VDD

VDD

VSS
VPB,VNB
0V
VNB
-VDD

Low Power Design Essentials ©2008 [Ref: H. Kawaguchi, VLSI Symp. 98] 9.
 Combining Body Biasing and Voltage Scaling

Active Standby
VPB VDD
WL
BL WL BLB 0V

VDD
VDD
VDD,VSS
0V

2VDD

VDD
VPB,VNB
VSS 0V
VNB
-VDD

Low Power Design Essentials ©2008 [Ref: A. Bhavnagarwala, SOC’00] 9.

 Combining Raised VSS and RBB

VPB

Supply Active Standby BL WL BLB

(V) (V)
VPB 1.0 1.75 VDD

VDD 1.0 1.0

VSS 0.0 0.65

VNB 0.0 0.0 VSS

VNB

28X savings in standby power reported

Low Power Design Essentials ©2008 [Ref: L. Clark, TVLSI’04] 9.

 Voltage Scaling in and Around the Bitcell
Large number of reported techniques
Voltage Approach
lower in active (e.g. DVS)
lower in standby
Bitcell VDD raise always
raise for read access
float or lower for write
float for read access
raise in standby
raise in standby [6][7][11][12][13][14][15]
Bitcell VSS raise or float for write
access
lower for read access
Wordline (WL) negative for standby
WL driver VDD lower in standby
Well-biasing change with mode
Bitline VDD lower for standby
Low Power Design Essentials ©2008
Source(s)
[1] K. Osada et al. JSSC 2001
[1]
[2][3][4][5][6][7] [2] N. Kim et al. TVLSI 2004
[8][9] [3] H. Qin et al. ISQED 2004
[5][9] [4] K. Kanda et al. ASIC/SOC 2002
[5][10]
[5] A. Bhavnagarwala et al. SymVLSIC 2004
[10]
[6] T. Enomoto et al. JSSC 2003
[7] M. Yamaoka et al. SymVLSIC 2002
[8] M. Yamaoka et al. ISSC 2004
[9] A. Bhavnagarwala et al. ASIC/SOC 2000
[16] [10] K. Itoh et al. SymVLSIC 1996
[11] H. Yamauchi et al. SymVLSIC 1996
[9]
[12] K. Osada et al. JSSC 2003
[4][10] [13] K. Zhang et al. SymVLSIC 2004
[14] K. Nii et al. ISSCC 2004
[7]
[15] A. Agarwal et al. JSSC 2003
[4][9] [16] K. Kanda et al. JSSC 2004
[12]
9.
 Periphery Breakdown

 Periphery leakage often not ignorable

– Wide transistors to drive large load capacitors
– Low VTH transistors to meet performance specs
 Chapter 8 techniques for logic leakage reduction
equally applicable, but …
 Task made easier than for generic logic because
of well-defined structure and signal patterns of
periphery
– e.g. decoders output 0 in standby
 Lower peripheral VDD can be used, but need fast
level-conversion to interface with array
Low Power Design Essentials ©2008 9.
 Summary and Perspectives

 SRAM standby power is leakage dominated

 Voltage knobs are effective to lower power
 Adaptive schemes must account for variation to
allow outlying cells to function
 Combined schemes are most promising
– e.g. Voltage scaling and ECC
 Important to assess overhead!
– Need for exploration and optimization framework, in
the style we have defined for logic

Low Power Design Essentials ©2008 9.

 References

Books and Book Chapters:

 K. Itoh, M. Horiguchi, and H. Tanaka, Ultra-Low Voltage Nano-Scale Memories, Springer 2007.
 T. Takahawara and K. Itoh, “Memory Leakage Reduction,” in Leakage in Nanometer CMOS
Technologies, S. Narendra, Ed, Chapter 7, Springer 2006.
Articles:
 A. Agarwal, L.Hai, K. Roy, “A single-V/sub t/ low-leakage gated-ground cache for deep
submicron,” IEEE Journal of Solid State Circuits, pp. 319-328, Febr. 2003.
 A. Bhavnagarwala, A. Kapoor, A.; J. Meindl, “Dynamic-threshold CMOS SRAM cells for fast,
portable applications,” Proceedings IEEE ASIC/SOC Conference, pp. 359-363, Sept. 2000.
 A. Bhavnagarwala et all, “A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic
power rails,” Proceedings IEEE VLSI Circuits Symposium, pp. 292-293, June 2004.
 L. Clark., M. Morrow, and W. Brown, “Reverse-body bias and supply collapse for low effective
standby power,” IEEE Transactions on VLSI, pp. 947-956, Sep 2004.
 T. Enomoto, Y. Ota, and H. Shikano, “A self-controllable voltage level (SVL) circuit and its low-
power high-speed CMOS circuit applications, “ IEEE Journal of Solid State Circuits, “ Vol. 38,
Issue 7, pp. 1220-1226, July 2003.
 K. Flautner et al., “Drowsy Caches: Simple Techniques for Reducing Leakage Power.,
Proceedings ISCA 2002, pp. 148-157, Anchorage, May 2002.
 K. Itoh et al, “A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node
and dynamic load, Proceedings VLSI Circuits Symposium, pp. 132-133, June,1996.
 K. Kanda, T. Miyazaki, S. Min, H. Kawaguchi, T. Sakurai, “Two orders of magnitude leakage
power reduction of low voltage SRAMs by row-by-row dynamic Vdd control (RRDV) scheme,”
Proceedings IEEE ASIC/SOC Conference, pp. 381-385, Sept. 2002.

Low Power Design Essentials ©2008 9.

 References (cntd)

 K. Kanda, et al., “90% write power-saving SRAM using sense-amplifying memory cell,” IEEE
Journal of Solid-State Circuits, pp.927 – 933, June 2004
 H. Kawaguchi, Y. Itaka and T. Sakurai, “Dynamic Leakage Cut-off Scheme for Low-Voltage
SRAMs,” Proceedings VLSI Symposium, pp. 140-141, June 1998.
 A. Kumar et al, “Fundamental Bounds on Power Reduction during Data-Retention in Standby
SRAM,” Proceedings ISCAS 2007, pp. 1867-1870, May 2007.
 N.Kim, K. Flautner, D. Blaauw, and T. Mudge, “Circuit and microarchitectural techniques for
reducing cache leakage power,” IEEE Transactions on VLSI, pp. 167-184, Feb 04 167-184
 Y. Nakagome et al.. “Review and prospects of low-voltage RAM circuits,” IBM J. R & D, vol. 47.
no. 516, pp. 525-552, Sep. /Nov. 2003.
 K. Osada, “Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation
scheme and a lithographically symmetrical cell, “ IEEE Journal of Solid State Circuits, pp. 1738-
1744, Nov. 2001.
 K. Osada et al, “16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-
induced multierrors,” IEEE Journal of Solid State Circuits, pp. 1952-1957, Nov. 2003.
 H. Qin, et al., “SRAM leakage suppression by minimizing standby supply voltage,” Proceedings
ISQED, pp. 55-60, 2004.
 H. Qin, R. Vattikonda, T.Trinh, Y. Cao, and J. Rabaey, “SRAM Cell Optimization for Ultra-Low
Power Standby,” Journal on Low Power Electronics, Vol. 2 No3, pp. 401–411, December 2006.
 J. Ryan, J. Wang, and B. Calhoun, "Analyzing and Modeling Process Balance for Sub-threshold
Circuit Design“ Proceedings GLSVLSI, pp. 275-280, March 2007.
 J. Wang and B. Calhoun, "Canary Replica Feedback for Near-DRV Standby VDD Scaling in a
90nm SRAM“, Proceedings Custom Integrated Circuits Conference (CICC), pages 29-32,
September 2007.

Low Power Design Essentials ©2008 9.

 References (cntd)
 J. Wang, A. Singhee, R. Rutenbar, and B. Calhoun, "Statistical Modeling for the Minimum
Standby Supply Voltage of a Full SRAM Array“, Proceedings European Solid State Circuits
Conference (ESSCIRC), pages 400-403, September 2007.
 M. Yamaoka et al. “0.4-V logic library friendly SRAM array using rectangular-diffusion cell and
delta-boosted-array-voltage scheme, Proceedings VLSI Circuits Symposium, pp. 13-15, June
2002.
 M. Yamaoka, et al, “A 300MHz 25/spl mA/Mb leakage on-chip SRAM module featuring process-
variation immunity and low-leakage-active mode for mobile-phone application processor,”
Proceedings IEEE Solid-State Circuits Conference, pp. 15-19, Febr 2004.
 K. Zhang et al., “SRAM design on 65nm CMOS technology with integrated leakage reduction
scheme,” Proceedings VLSI Circuits Symposium, 2004, pp. 294-295, June 2004.

Low Power Design Essentials ©2008 9.