INTRODUCTION

 8085 was introduced by Intel™ in late 1975.

 It’s an 8-bit microprocessor, meaning that it’s ALU can
perform operation on 8-bits simultaneously.
 It operates on a single 5V±5% supply.
 It can operate with external crystal frequency up to 6MHz.
 The external crystal frequency is internally divided by 2.
 So, 8085 can operate with a maximum speed of 3MHz.
 8085 has on chip oscillator which added to its huge popularity
over its predecessor 8080.
 Its compatible processor is Zilog™ Z80.
 Together, 8085 and Z80 makes highest number (over 10-
million) of 8-bit processor still working in real time
situations.
 SIMPLIFIED LOGIC DIAGRAM
X1 8
D0 – D7
CRYST
AL X2
8
CLK OUT A0 – A7

READY
8
8085 A8 – A15
RESETI
N CPU
RESET
OUT
RD

Vcc WR

Gnd IO/M
 8085 MEMORY RANGE
 8085 has 16-bit address bus (A0 – A15).
 It means, it can access 216 memory locations.

216 = 26 X 210 = 26 X 1K = 64 X 1K = 64K
 So, 8085 can access up to 64K memory locations.
 At every memory location, 8-bits i.e. 1-Byte is stored.
 Hence, 8085 can access up to 64KB of memory data.
 The memory address range is
0000 0000 0000 0000B 0000H 00 00H
0000 0000 0000 0001B 0001H 00 01H Lower Address Byte
: : A – A = FEH
7 0

: :
1111 1111 1111 1110B FFFEH FF FEH
1111 1111 1111 1111B FFFFH
Higher Address Byte
FF FFH
A – A = FFH
15 8
SIMPLIFIED LOGIC DIAGRAM (CONTD.)
8
X1 A8 – A15
CRYST
AL X2

CLK OUT 8
AD0 – AD7
READY
8085
RESETI ALE
N CPU
RESET
OUT
RD

Vcc WR

Gnd IO/M
 DEMULTIPLEXING AD BUS
8
X1 A8 – A15
A8 – A15
CRYST
AL X2
A0 – A 7
CLK OUT LATC
H
READY
ALE
EN
RESETI D0 – D 7
N AD0 – AD7
RESET
OUT 8085 RD

Vcc
CPU
WR

Gnd IO/M
DEMULTIPLEXING AD BUS
 LOGIC DIAGRAM

Vcc
AD0 – AD7
X1
Lower 8 - bit Address/Data Bus.
X2
RESET IN
READY A8 - A15

TRAP (RST 4.5) Higher 8 - bit Address Bus.

RST 7.5
ALE
RST 6.5 8085 RD
RST 5.5
WR
INTR
IO/M
INTA
S1
HOLD
S0
HLDA
RESET OUT
SID
CLK OUT
SOD
Gnd
 SIMPLIFIED ARCHITECTURE
INTERRUP
B C T SERIAL I/O
D E CONTROL CONTROL
H L
IR W Z
INCREMENTE
R/ A M_TMP
CRYST DECREMENT
AL ER
M2
SP M1
ALU
X1 X2 PC F COUT C3 M0
TIMING
and
CONTROL UNIT FLAGS
C0 C1 C2 Cn

AR (H) AR (L) DR
8 8 8
A8 – A15 A0 – A7 D0 – D7
INTERNAL ARCHITECTURE
 FLAGS
b7 b6 b5 b4 b3 b2 b1 b0

SF ZF X AC X PF X CY

SIGN 2’s Complement Sign of the Result

FLAG SF =1, If MS bit of the Result is 1, else SF=0.

ZERO Is the Result of ALU 0 or not?

FLAG ZF =1, When result ALU is 0 other wise ZF=0.

AUXILIARY
Auxiliary Carry Generated during ALU operation
CARRY
FLAG or not?
AC=1, A carry is generated from bit b3 to b4
during ALU operation other wise AC=0.
 FLAGS
b7 b6 b5 b4 b3 b2 b1 b0

SF ZF X AC X PF X CY

PARIT Is Parity of 1’s in Result ODD/EVEN?

Y PF =1, When Even numbers of 1s in the ALU
FLAG result, other wise PF=0.

Carry Generated/Borrow Required during ALU

CARRY
FLAG operation or not?
CY=1, If a carry is generated from MS bit OR A
Borrow was required by the MS bit during
ALU operation, other wise CY=0.
 FLAGS (CONTD.)
ADD 23H and 15H

23 = 0 0 1 0 0 0 1 1
15 = 0 0 0 1 0 1 0 1
38H 0 0 1 1 1 0 0 0
X X
Result is NON- ZERO ,
ZF = 0.
No CARRY from There are 3 1s, PF = 0.
MS bit, CY = 0.

There is NO CARRY from

MS bit of the SUM is 0, bit b3 to bit b4, AC = 0.
SF = 0.
 FLAGS (CONTD.)
ADD 69H and 18H

69 = 0 1 1 0 1 0 0 1
18 = 0 0 0 1 1 0 0 0
81H 1 0 0 0 0 0 0 1
X
Result is NON- ZERO ,
ZF = 0.
No CARRY from There are 2 1s, PF = 1.
MS bit, CY = 0.

There is a CARRY from

MS bit of the SUM is 1, bit b3 to bit b4, AC = 1.
SF = 1.

Why result of SUM appears Negative (i.e. SF=1)

 FLAGS (CONTD.)
ADD CB and E9

CB = 1 1 0 0 1 0 1 1
E9 = 1 1 1 0 1 0 0 1
1 1 0 1 1 0 1 0 0
Result is NON- ZERO ,
ZF = 0.
There is a CARRY There are 4 1s, PF = 1.
from MS bit, CY = 1.

There is a CARRY from

MS bit of the SUM is 1, bit b3 to bit b4, AC = 1.
SF = 1.