COMPUTER ARCHITECTURE COE 485

PRESENTED BY: EKE CHIJIOKE DAVID

6th October 2011.

Scope

Direct Mapped Cache Set Associative Mapping Example of Cache Organization

Example on Associativity and Cache miss rate

Direct Mapping

Each address has a specific place in the cache.

Direct Cache Addressing

The lower log2(line size) bits define which byte in the block The next log2(number of lines) bits defines which line of the cache The remaining upper bits are the tag field.
TAG LINE OFFSET

Cache Constants

cache size / line size = number of lines log2(line size) = bits for offset log2(number of lines) = bits for cache index remaining upper bits = tag address bits

Example direct address

Assume you have 32 bit addresses (can address 4 GB)

64 byte lines (offset is 6 bits)

32 KB of cache
Number of lines = 32 KB / 64 = 512 Bits to specify which line = log2(512) = 9 17bits 9bits 6bits
TAG LINE OFFSET

A hit occurs if the tag field of line in the cache contains the value in the tag, otherwise a miss occurs. If a hit occurs then the offset field is used to access the item from the cache line.

Practice Problem
Q: How many bits are in the tag, line and offset fields if the a mapped using Direct Mapping

24 bit addresses 64K bytes of cache 16 byte cache lines

a. tag=4, line=16, offset=4 b. tag=4, line=14, offset=6 c. tag=8, line=12, offset=4 d. tag=6, line=12, offset=6

Merits & Demerits

Only one comparator is required, so this will be a less expensive system than the fully associative system. The main disadvantage of the direct mapped system is that a given block from main memory can only be placed into a specific line within the cache.

Set Associative Mapping

Each address can be in any of a set of cache locations. Combines the simplicity of direct mapping with the flexibility of associative mapping

Terminologies in Set Associative Mapping

Ways: the cache is divided into a number of partitions (called ways) each of which contains the same number of lines Set: The corresponding lines in all of the ways constitute a set. Associativity: The associativity is the number of lines per set.

Q: What happens when a 3rd block is brought into a 2-way Set associative cache?
A: One of the lines would have to be reused. Hence a cache line replacement algorithm would have to be implemented.

Common Replacement Algorithms

FIFO: First-In-First-Out LRU: Least Recently Used Random

Cache Constants
When the processor wants an address, it indexes to the set and then searches the tag fields of all lines in the set for the desired address.

n = cache size / line size = number of lines b = log2(line size) = bit for offset

w = number of lines / set

s = n / w = number of sets

Example: A 64K cache organized as a 2-way set associative cache is to be employed on a system that contains 16 Megabytes of main memory. Each cache line contains four 32-bit words. a) What is the proper address format? There are two lines per set. Each line contains 16 bytes. The total number of sets is (64K/2)/16 = 2048. Therefore the set field requires 11 bits, the offset requires 4 bits and the remaining 24-11-4 = 9 bits are used as the

Example on Cache organization Case Study: an 8-cache.

The total size of the cache in block = the number of sets x the associativity (or set size). For a fixed cache size, increasing the associativity decreases the number of sets, while the number of elements per set increases. A direct mapped cache can be thought of as having a number of sets equal to the number of blocks in the cache. A fully associative cache has one set with a number of elements equal to the number of blocks in the cache.

Example on Associativity and Cache Miss Rate

There are 3 small caches, each containing four one-word blocks. One cache is direct mapped (i.e. on-way associative), a second is two-way set associative, and the third is fully associative. If an LRU replacement policy is used when required, find the number of misses for each cache organization given the following sequence of block addresses: 0,8,0,6,8.

References

Cache Mapping: COMP375 Computer Architecture and Organization by C.S Williams. cswilliams.ncat.edu/COMP375/CacheMapping.p df Section 2. Memory Architecture: Memory Hierarchy, Cache Memory, SRAM, and Power Management University of Rhode Island. http://www.ele.uri.edu/courses/ele408/syallabus/ Lectures.pdf Cache memory by Tatsiana Gomova. www.cs.sjsu.edu/~lee/cs147/Cache%20memory. ppt COE 485: Computer Architecture Dr K. Diawuo.