S Note Power Sequence Presentation

30-Sep , 2003
Charles YM Chen
NB Product Engineering
 S Note Block Diagram
Aug 08 '26 Clock Generator
ICS950813
3
Intel Mobile CPU
Banias/Dothan S Note-1 Block Diagram
4,5,6 03209-SD-Final
Keyboard Light AGTL+ FSB 400MHz

UNBUFFERED LVDS
12.1'' XGA LCD
On-Board DDR
SODIMM x 8
Intel 18
11,12,13,15,16 Motara-GM Plus
Media Slice 46
200-PIN DDR SODIMM DDR 200/266/333 AGTL+ CPU I/F RGB CRT
CRT SELECTION
DDR Memory I/F 17 CRT Port 19
UNBUFFERED INTEGRATED GRAHPICS
DDR SODIMM
LVDS, CRT I/F MediaBay I/F
Socket
14,15,16 7,8,9,10 RICOH SD
R5C5811 Socket
Cardbus + SD Card 30
Thermal Sensor Power Switch
Hub-LINK 66MHz
LM83+LM26+DS75 TPS2205
Secondary IDE 28
47 SMBus Media ATA 66/100
PCMCIA
Slice 46 SLOT
Intel 26,27
ATMEL Primary IDE PCMCIA I/F 29
AT24RF08CN
48 HDD ATA 66/100 ICH4-M
23
USB 2.0 (2+2+2) PCI Bus / 33MHz
LINE OUT ETHERNET (10/100Mb)
OP AMP AC97 2.2
MAX9750 ATA 66/100 Intel Ethernet
39
ACPI 1.1 Giga LAN Mini-PCI
Int. MIC LPC I/F
802.11a/b/g
82541EX
31,32 34
PCI/PCI BRIDGE
AC97 CODEC INT. RTC
ATMEL
AT93C46
OR
AD1981B
MIC IN 36,37,38 Intel Ethernet
AC LINK LAN MII 10/100 PHY RJ45 PMH-4
CONN G/A
20,21,22 82562EZ 33
31,32 43
CDC
Modem/Bluetooth
RJ11 CH4 USB 2.0
LPC Bus / 33MHz
CONN
33 35
KBC NS FIR & LPC SW FWH LPC Debug TCPA
USB 1 H8S/2161B PC87382 Board Conn Chip
24,25 SST-49LF008
CH2,3
41 45 40 41 44
USB 2
24,25
LPC Bus

Int. KB FIR
Secondary IDE USB Hub Track point IV IRMS6452 NX SIO
SMSC 42 39 PC87392
USB20H04

Line In Line Out UltraBay PS/2 x2 CRT RJ11 RJ45

MAX3243
HDD, Optical Drives RS232 Transceiver
2nd Battery
Stereo Speaker x 2 USB x 3 Media Slice COM Port Parallel Port DC-IN 46

2 S Note Power Sequence Presentation

 FET PolySW
Nch 1.5A USB_PWR1

S Note Power on Sequence

Docking
FET PolySW
Connector USB_PWR2
VDD15 Nch 1.5A
1
FET MAX1683 LP3958 MICVCC 11
DOCK-PWR16_F 4
Pch VCC_FAN
VCC5M FET VCC5B Fuse FET
3 Nch 0.75A Pch
10
Fuse FET FET VINT16
7A Pch Nch
MAX1977 4
10
VCC3M FET
12 VCC3B
DC-IN Nch
BPWRG 11
Connector
APWRG 12 MAX8880 VCCACPU
Tsurumai 4 MPWRG FET
2 14 VCC3AUX 6
VCC3SW Pch
VREGIN16 MAX1907 VCCCPUCORE Fuse FET VCC3P
2
15 2A Nch
IM VPOK VR_PWRGD 4.1
H8 VCC1R8M
7 VTT_PWRG 9 10 MAX1935
7 PWRSW#
PWRSW_H8# VCC2R5A VCC1R25B
LP2996
DDR_VREF 10
Power VCPU_CORE_ON 8 11
MAX1845 4 VCC1R5M FET VCC1R5B
Button 7 B_ON 8
Nch
PWRSWITCH# +PWRON 8 MAX1845_VREF 6
ICH_SLP_S4# 5 PMH4 PM_SLP_S5# 7 FET VCC1R5AUX
ICH_SLP_S3# 5 PM_SLP_S3# 7 Nch
11 11
FET
VCCCPUIO VCCGMCHCORE
MAX1992 Nch
MAX4245
SLP_S4# ICH_SLP_S4# 5 13

MPWRG
SLP_S3#
RSMRST#
ICH_SLP_S3# 5 VTT_PWRG
PCIRST# PCIRST# 16
BPWRG PWROK
CC_CPUPWRGD
PWRSW_H8# PWRBTN#
17
VR_PWRGD ICH4M 6
Fuse FET VCCGBECOREAUX
2A Nch VBL16 VCC3M
MAX1935
CC_CPUPWRGD PWRGOOD 6
VCCGBEIOAUX
CPU 19 VCC1R8M
FET
GTL_ADS# Nch
GTL_CPURST# MONTARA GM+ (Kenai2-32)
18
PWROK CPURST#
For Ethernet Controller
BPWRG GTL_CPURST#

3 S Note Power Sequence Presentation

 Power on seuqence table
S Note Power Sequence Table (adapter in)
Signal name Description measure point
1 DOCK-PWR16-F U46 Pin 1,2,3 U46 Pin1,2,3
2 VREGIN16 Dock-PWR16-F=>D42 pin3 D42 Pin3
VCC3SW output pin made from the internal regulator. U28 Pin 59
3 CV16  Vgs of U47 ＜-4.5VU46 in saturation region => U46 pin 5,6,7,8,output CV16 U46 Pin 5,6,7,8
VINT16 R50 pin2
4 EXTPWR_PMH# Power on logic in PMH4 U36 Pin 73
VCC3M_ON MAXIM1845 ON2, TSURUMAI 3M_ON, MAXIM1935 SHDN# R696 Pin2
VCC5M_ON MAXIM 1977 ON3&ON5, TSURUMAI 5M_ON R329 Pin2
VCC3M OUT3 of MAXIM 1977 U85 Pin 22
VCC5M OUT5 of MAXIM 1977 U85 Pin 21
VCC1R5M OUT2 of MAXIM 1845 U43 Pin 15
VCC1R8M OUT of MAXIM 1935 U42 Pin 7,8
MPWRG Output for VCC3M/VCC5M Power Good Signal (Open-Drain) U28 Pin51
5 ICH_SLP_S3# ICH_SLP_S3# is for power plane control U36 Pin 20
ICH_SLP_S4# ICH_SLP_S4# is for power plane control U36 Pin 74
6 AUX_ON TSURUMAI RD3_ON & RD4_ON, MAXIM1935 SHDN#, U36 Pin 88
VCC3AUX VCC3AUX power by FDC658P U40 Pin4
VCCGBECOREAUX OUT of MAXIM 1935 U60 Pin 7,8
GBE_AUXPWRG POK of MAXIM 1935 U60 Pin 3
VCCGBEIOAUX_DRV RD3_DRV of TSURUMAI R206 Pin 2
VCCGBEIOAUX VCCGBEIOAUX power by FDN359AN Q64 Pin 2
VCC1R5AUX_DRV RD4_DRV of TSURUMAI U28 Pin 31
VCC1R5AUX VCC1R5AUX power by FDN359AN Q22 Pin 2
7 PWRSWITCH# Power button D21 Pin 1
PWRSW# Bus control outputs, regardless of the input/output direction indicated U22 Pin 20
PWRSW_H8# Bus control outputs, regardless of the input/output direction indicated U22 Pin 19
ICH_SLP_S3# ICH_SLP_S3# is for power plane control U36 Pin 20
Outputted by PMH4. It shuts off power to all non-critical systems when in S3
PM_SLP_S3# U36 Pin 71
(Suspend To RAM),S4 (Suspend to Disk), or S5 (Soft Off) states.
ICH_SLP_S4# ICH_SLP_S4# is for power plane control U36 Pin 74
Outputt by PMH4, The signal is used to shut power off to all non-critical systems
PM_SLP_S5# U36 Pin 72
when in the S5 (Soft Off) states.
8 +PWRON MAXIM1845 ON1, TSURUMAI 3A_ON U36 Pin 63
MAXIM8880 SHDN#, LP2996 SD#, MAXIM4245 SHDN#, MAXIM1992
B_ON R350 Pin 2
SHDN#, TSURUMAI 3B_ON, 5B_ON, RD2_ON
VCPU_CORE_ON MAXIM1907 SHDN# D55 Pin2
9 VCC2R5A OUT1 of MAXIM 1845 U43 Pin1
4 S Note Power Sequence Presentation
 Power on seuqence table
10 DDR_VREF Voltage of DDR SODIMM U7 Pin 4
VCC1R25B VTT & VSENSE of LP2996 TC12
VCC3B VCC3B power by FDC655AN Q72 Pin 4
VCC5B VCC5B power by FDC655AN Q31 Pin 4
11 VCCACPU OUT by MAXIM8880 U41 Pin3
VCCGMCHCORE Core power of Motara-GM Plus TC13 Pin 1
MICVCC VOUT of LP3985 U37 Pin 5
VCCCPUIO CPU I/O power by MAXIM 1992 TC3
VCC1R5B_DRV RD2_DRV of TSURUMAI U28 Pin 35
VCC1R5B VCC1R5B power by FDC655AN Q28 Pin 4
12 MPWRG Output for VCC3M/VCC5M Power Good Signal (Open-Drain) U28 Pin51
APWRG Output for VCC3A Power Good Signal (Open-Drain) U28 Pin 49
BPWRG(PWROK) Output for VCC5B/VCC3B Power Good Signal (Open-Drain) D30 Pin 1
13 VTT_PWRG CPU I/O power good U59 Pin 4
14 VCORE_ON MAXIM1907 SHDN# U12 Pin 7
VCCCPUCORE CPU Core power TC4, TC5, TC6
15 VR_PWRGD MAXIM 1992 IMVP OK U12 Pin 37
ICH4 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH4
16 PCIRST# asserts PCIRST# during power-up and when S/W initiates a hard reset sequence R238 Pin1
through the RC (CF9h) register
This signal should be connected to the processor’s PWRGOOD input. allow for Intel
17 CC_CPUPWRGD ® SpeedStep™ technology support, this signal is kept high during an Intel SpeedStep R259 Pin 2
technology state transition to prevent loss of processor context.
The CPURST# pin is an output from the MGMCH. The MGMCH asserts
18 GTL_CPURST# CPURST# while RSTIN# (PCIRST# from ICH4) is asserted and for approximately R630 Pin 2
1 ms after RSTIN# is deasserted.
The processor bus owner asserts ADS# to indicate the first of two cycles of a request
19 GTL_ADS# Test pad
phase.
20 LPC_FRAME# LFRAME# indicates the start of an LPC cycle, or an abort. U36 Pin 4
TRDY# indicates the ICH4's ability, as a Target, to complete the current data phase
21 P_TRDY# of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is RN41 Pin2
completed when both TRDY# and IRDY# are sampled asserted.
TRDY# indicates the ICH4's ability, as an Initiator, to complete the current data
21 P_IRDY# phase of the transaction. It is used in conjunction with TRDY#. A data phase is RN41 Pin3
completed on any clock that both IRDY# and TRDY# are sampled asserted.
The current Initiator drives FRAME# to indicate the beginning and duration of a PCI
21 P_FRAME# transaction. While the Initiator asserts FRAME#, data transfers continue. When the RN41 Pin4
Initiator negates FRAME#, the transaction is in the final data phase.

5 S Note Power Sequence Presentation

 DOCK-PWR16_F & VREGIN 16
DOCK-PWR16-F U46 Pin 1,2,3 U46 Pin1,2,3
VREGIN16 Dock-PWR16-F=>D42 pin3 D42 Pin3
CV16  Vgs of U47 ＜ -4.5VU46 in saturation region => U46 pin 5,6,7,8,output CV16 U46 Pin 5,6,7,8

DOCK_PWR16 DOCK-PWR16_F

JK1 U46 CV16

F1
1 1 2 1 8

3 R451007 2 7

1
1

1
2 C2 R393 3 6
4 C1 SC1000P50V 10R2 C6 C5
2

2
5 SCD1U50V3KX For EMI 4 5 SC1000P50V SCD1U50V3KX

1
DC-JACK70 Please close to JK4 R394

1
22.10037.681 470KR2 TPC8109-P
R395 C4

2
470KR2F SCD47U25V6KX

2
C7 1 2 DY-SC4D7U25V6KX

NO ASM
VREGIN16

DOCK-PWR16_F
F15 D42
1 2 2

FUSE-D5A32V 3

DAN222

6 S Note Power Sequence Presentation

 VCC3SW
VCC3SW output pin made from the internal regulator. U28 Pin 59

7 S Note Power Sequence Presentation

 VCC3M_ON & VCC5M_ON
EXTPWR_PMH# Power on logic in PMH4 U36 Pin 73
VCC3M_ON MAXIM1845 ON2, TSURUMAI 3M_ON, MAXIM1935 SHDN# R696 Pin2
VCC5M_ON MAXIM 1977 ON3&ON5, TSURUMAI 5M_ON R329 Pin2

Spec:

VCC3M_ON(M_ON1) to VCC5M_ON(M_ON2)
is 10ms~20ms

8 S Note Power Sequence Presentation

 VCC3M & VCC5M
VCC3M & VCC%M power by MAXIM 1977
VIN T16 D C BATOU T_MAX1977
3A (4.5A) MAX1977_LD O5 MAX1977_VC C

R 756 R 719 R 740

1 2 1 2 MAX1977_V+ 1 2

1
0R 1206 3D 3R 5 49D 9R 3F
3D 3V_D C _S5 VC C 3M C 725 C 742
SC D 1U 25V3KX VC C 5M

2
R 727 SC 1U 10V3ZY 5V_D C _S5
1 2
D C BATOU T_MAX1977

1
G12 D 70 G19
1 2 3D 3R 5 C 731 BAW56LT1 2 1

2
SC 4D 7U 25V6KX
GAP-OPEN GAP-OPEN
G13 G18
1 2 2 1
1

1
MAX1977_BST3 MAX1977_BST5

SC 10U 25VKX-2

SC 10U 25VKX-2

SC 10U 25VKX-2

SC 10U 25VKX-2

SC D 1U 25V3KX
GAP-OPEN C 419 C 753 C 751 C 755 C 744 C 749 C 756 GAP-OPEN
2

5
6
7
8

2
G14 SC 4D 7U 25V-1-U SC D 1U 25V3KX G17

1
1 2 2 1

D
D
D
D
C 702 R 711 R 750 C 746
GAP-OPEN SC D 1U 16V3KX 10R 3 U 85 10R 3 SC D 1U 16V3KX GAP-OPEN

20

17
G15 G20

2
1 2 CLOSE TO U 90 2 1

V+

VC C
CMOS SI4800

G
S
S
S
GAP-OPEN U 91 28
MAX1977_BST3R 14 MAX1977_BST5R GAP-OPEN
1 BST3 BST5
PLFC0745P

4
3
2
1
R 746 R 754 3 L14 4
2 8 1977_D H 32 1 MAX1977_D H 3 26 16 MAX1977_D H 5 1 2 1977_D H 5
L15 DH3 DH5
3.6A 5A
1 2 7 0R 3-U MAX1977_LX3 27 15 MAX1977_LX5 0R 3-U 2 1
R 747 LX3 LX5 IN D -4U H
IN D -3D 9U H 6 3 1977_D L3 2 1 MAX1977_D L3 24 19 MAX1977_D L5
D L3 D L5
U89 use the FDS6690A symbol.

1
5 4 0R 3-U 22 21 R 741 0R 3-U TC 17 TC 18
OU T3 OU T5

5
6
7
8

ST100U 10VM

ST100U 10VM
2

2
SI4814D Y MAX1977_FB3 7 9 MAX1977_FB5 D 37 C 728

D
D
D
D
C 729 FB3 FB5 SSM14 SC 47P
ST150U 6D 3VD M-5
1

2
TC 10 SC 47P R 388 U 89

2
2 1 TPC 8014-N
2

1
3 R 753

1977_D L5
MAX1977_ON 3
R 721 D 015R 2512F 4 ON 3 10 1 2 R 391 R 736
MAX1977_ON 5
ON 5 PR O#

S
S
S
G
1

1
2MR 3 64.R 0155.L02 13 1 2 2MR 3 R 739
C 705 6 C S5 100KR 3 15KR 3F C 740
SH D N #
2

4
3
2
1

2
SC 100P50V2J N R 718 D 015R 2512F SC 100P50V2J N
7K32R 3F 64.R 0155.L02
2

11 MAX1977_ILIM5
ILIM5
43,47,59 PW R SH U TD OWN # MAX1977_VC C
1

1
R 361 MAX1977_C S3 1
1 2 C S3 5 MAX1977_ILIM3 R 752
R 710 1KR 2 ILIM3 1 2 R 731
These components should be
located near by MAX1977 10K7R 3D 10KR 3F
2

2
R 360 8 2 110KR 3F VC C 5B
1 2 R EF PGOOD
43 VC C 5M_ON R 748
1KR 2 1 2 These components should be

1
12 23 located near by MAX1977
SKIP# LD O3 GN D 110KR 3F

LD O5
VR EF2 MAX1977_R EF R 712
R 362 10KR 2
SKIP# = GND : SKIP MODE

2
1 2 MAX1977EEI-U
SKIP# = REF/FloatING : Ultrasonic
25

18
MAX1977_PWR GD TP12
VC C 3M 100KR 2 TPAD 30
MODE MAX1977_LD O3 MAX1977_LD O5 VL5
(25KHz min)
2
1

C 715 ILIM5: 5*36.5 / (36.5+110) = 1.245V

1

C 360 R 341 SC D 22U 10V3KX R 371 1 2 0R 3-U

1.245 / 15 = 8.3A
2

SC D 1U 10V2KX 100KR 3

1
1
2

ILIM3: 5*22.6 / (22.6+110) = 0.8521V

U 80 MAX1977_SKIP# C 377 C 392 R 751 R 749
SC D 1U 10V2KX 85 / 15 = 5.6A
2

1 5 SC 10U 10V5ZY 36K5R 3F 22K6R 3F

NC VC C
3

2
2
2 D
41,43,56 PM_SLP_S3# A
3 4 PM_SLP_S3 1 Q73
GN D Y 2N 7002
G
2

N C 7SZ14-U S
100mA MAX. each
USE 73.7SZ14.0AH SYMBOL TO REPLACE 73.7SZ14.0AHN1 SYMBOL

9 S Note Power Sequence Presentation

 VCC3M & VCC5M
VCC3M OUT3 of MAXIM 1977 U85 Pin 22
VCC5M OUT5 of MAXIM 1977 U85 Pin 21

10 S Note Power Sequence Presentation

 VCC1R5M & VCC1R8M

VCC1R8M power by MAXIM 1935

VCC1R5M power by MAXIM 1845 VCC3M VCC1R8M

VINT16

1
VL5 U42
C386

2
SC1U10V3KX 1 8
IN OUT
1

1
C378 C389 2 7
IN OUT

1
2

SC1U10V3KX 2 SC1U25V5ZY
1

C383 C381
4 6 R345
2

SCD01U25V2KX SCD01U25V2KX
43,56 VCC3M_ON SHDN# SET 105KR3F

1
VL5
Close to pin21 Close to pin4
5 C711
GND

2
3 9 SC10U10V-3-U
3

POK GND

1
D73 R725
BAW56LT1 20R2F
2

MAX1845_BST2 MAX1935ETA R353

84K5R3F

2
1

R356
100KR3F
1

C390
2

1
SC1U10V3KX
C723
1

2
SCD01U25V2KX
R363

1
47K5R3F R366
0R3-U C710
22

21
4

2
SC4D7U25V-U
C367
V+

1
9 13 SCD1U25V3KX
VCC

VDD

UVP ILIM2 2 C726

3 19 MAX1845_BST2R SCD1U25V3KX
ILIM1 BST2
U82
25 1
BST1 R704
26 18 MAX1845_DH2 1 2 1845_DH2 8 2
27 DH1 DH2 17
LX1 LX2
MAX1845_LX2 1.5V / 4A
24 20 MAX1845_DL2 0R3-U 7
DL1 DL2 R732 PLFC0745P VCC1R5M
28 16 1 2 1845_DL2 3 6
CS1 CS2 L11
0R3-U 4 5 1 2
1 15
OUT1 OUT2
1

1
SI4814DY IND-3D8UH
2 14 TC16 R343
FB1 FB2
2
ST220U4VDM-6 4K99R3F-1
11 12 Rds(on) = 26.5 mohm
ON1 ON2

2
1

5 7
MAX1845_VREF 10 TON PGOOD
REF

1
8 D64 D65
6 OVP B220LFA B220LFA
GND

SKIP#
2

R344
1

U43 10KR3F

2
23

C374 MAX1845EEI-U
2

SC1U10V3KX
1

C369
2

SC33P50V2JN

VCC3M_ON 43

11 S Note Power Sequence Presentation

 VCC1R5M & VCC1R8M
VCC1R5M OUT2 of MAXIM 1845 U43 Pin 15
VCC1R8M OUT of MAXIM 1935 U42 Pin 7,8

12 S Note Power Sequence Presentation

 MPWRG
In the block of M_PGS, the voltage of VCC5M and VCC3M are monitored by the internal analog comparator respectively, each state
is supplied to M_PGS output. The terminal is Open drain structure.
The operation of detection is started when both 5M_ON and 3M_ON are equal to High. The analog Comparator has hysteresis
voltage and generate high signal when the following condition are satisfied.
Greater than 4.461V(Typ.) at power on stage of "VCC5M" （ Rising Edge ） and lower than 4.311V (Typ.) at the shut down stage
(Falling edge) after 47.5ms +/- 2.5ms
Greater than 2.943V(Typ.) at power on stage of "VCC3M" （ Rising Edge ） and lower than 2.793V (Typ.) at the shut down stage
(Falling edge) after 47.5ms +/- 2.5ms
"L" output is "VCC5M" ＝ 4.311V （ Typ. ）， "VCC3M" ＝ 2.793V （ Typ. ）

13 S Note Power Sequence Presentation

 MPWRG
MPWRG Output for VCC3M/VCC5M Power Good Signal (Open-Drain) U28 Pin51

Spec:VCC3/5M Power to MPWRG is 47.5+/- 5ms

14 S Note Power Sequence Presentation

 ICH_SLP_S3# & ICH_SLP_S4#
ICH_SLP_S3# ICH_SLP_S3# is for power plane control U36 Pin 20
ICH_SLP_S4# ICH_SLP_S4# is for power plane control U36 Pin 74

Spec: Depend on ICH4M spec , the SLP_S4# and SLP_S3# should rise up after Power on. SLP_S3#

to SLP_S4# is 1 RTCCLK~2RTCCLK. (1RTC clock is approximately 32 us.)

15 S Note Power Sequence Presentation

 VCC3AUX & VCCGBECOREAUX

VCC3AUX power by FDC658P VCCGBECOREAUX power by MAXIM 1935

VCC3M VCC3AUX
VCC3M
U40
6 D D 1 VCCGBECOREAUX
5 D D 2

1
4 S G 3 U60

1
C524
1

FDC658P R708

2
SC1U10V3KX 1 8
IN OUT
1

47KR2 2 7
C693 R705 IN OUT

1
2

SCD1U10V2KX 100KR2
2

4 6 R536
43,58 AUX_ON SHDN# SET 42K2R3F

1
1

5 C523
GND

2
R706 3 9 SC10U10V-3-U
43 GBE_AUXPWRG POK GND

1
1KR2
2

MAX1935ETA R534
3

D 84K5R3F
1 Q30

2
43,59,60 AUX_ON 2N7002
G
2

16 S Note Power Sequence Presentation

 VCC3AUX & VCCGBECOREAUX
VCC3AUX VCC3AUX power by VCC3M and FDC658P U40 Pin4
VCCGBECOREAUX OUT of MAXIM 1935 U60 Pin 7,8
GBE_AUXPWRG POK of MAXIM 1935 U60 Pin 3

17 S Note Power Sequence Presentation

 VCCGBEIOAUX & VCCGBEIOAUX_DRV
VCCGBEIOAUX_DRV RD3_DRV of TSURUMAI R206 Pin 2
VCCGBEIOAUX VCCGBEIOAUX power by FDN359AN Q64 Pin 2

VCC1R8M VCCGBEIOAUX
Q64
FDN359AN

3 2

S
D

1
R578

1
270R3

2
2
D57
RB521S-30

1
59 VCCGBEIOAUX_DRV

1
1
C586 R579

2
SCD1U25V3KX 470KR3

2
18 S Note Power Sequence Presentation
 VCC1R5AUX & VCC1R5AUX_DRV
VCC1R5AUX_DRV RD4_DRV of TSURUMAI U28 Pin 31
VCC1R5AUX VCC1R5AUX power by FDN359AN Q22 Pin 2

VCC1R5M VCC1R5AUX
Q22
FDN359AN

3 2

S
D

1
R300

1
270R3

2
2
D31
RB521S-30

1
59 VCC1R5AUX_DRV

1
1
C298 R301

2
SCD1U25V3KX 470KR3

2
19 S Note Power Sequence Presentation
 Press Power Button
PWRSWITCH# Power button D21 Pin 1
PWRSW# Bus control outputs, regardless of the input/output direction indicated U22 Pin 20
PWRSW_H8# Bus control outputs, regardless of the input/output direction indicated U22 Pin 19

20 S Note Power Sequence Presentation

 Press Power Button
ICH_SLP_S3# ICH_SLP_S3# is for power plane control U36 Pin 20
Outputted by PMH4. It shuts off power to all non-critical systems when in S3
PM_SLP_S3# U36 Pin 71
(Suspend To RAM),S4 (Suspend to Disk), or S5 (Soft Off) states.

21 S Note Power Sequence Presentation

 Press Power Button
ICH_SLP_S4# ICH_SLP_S4# is for power plane control U36 Pin 74
Outputt by PMH4, The signal is used to shut power off to all non-critical systems
PM_SLP_S5# U36 Pin 72
when in the S5 (Soft Off) states.

22 S Note Power Sequence Presentation

 +PWRON & B_ON & VCPU_CORE_ON
+PWRON MAXIM1845 ON1, TSURUMAI 3A_ON U36 Pin 63
MAXIM8880 SHDN#, LP2996 SD#, MAXIM4245 SHDN#, MAXIM1992
B_ON R350 Pin 2
SHDN#, TSURUMAI 3B_ON, 5B_ON, RD2_ON
VCPU_CORE_ON MAXIM1907 SHDN# D55 Pin2

Spec: From +PWRON to B_ON is 10ms~20ms

23 S Note Power Sequence Presentation

 VCC2R5A
VCC2R5A power by MAXIM 1845
VINT16
R738
1 2 VINT16_MAX1845_2

0R1206

VL5

1
C383 C378

2
SCD01U25V2KX

SC1U10V3KX
1

1
C399 C400 C403 R725

2
SC4D7U25V-1-U SC4D7U25V-1-U SCD1U25V3KX

3
20R2F

2
D73
BAW56LT1

1
C732

1
2

SCD01U25V2KX

1
7.8 * 1.5 = 11.7
11.7 * 22 = 257mV R730

1
100KR3F C390 C381 C389
ILIM1: 5*100 / (100+100) = 2.5V

1
2
OCP1: 250 / 22 = 11.36A

2
SC1U10V3KX

SC1U25V5ZY
SCD01U25V2KX
1
R735
100KR3F

22

21
2

4
U43

8
7
6
5

V+
9 13

VCC

VDD
D
D
D
D
UVP ILIM2
2.5V / 7.8A D34
2 1 U84 3 19
SI4800 ILIM1 BST2
B220LFA R722 25
VCC2R5A BST1

S
S
S
G
D67 PLFC1045P 1 2 26 18
2 1 27 DH1 DH2 17
LX1 LX2

1
2
3
4
24 20
DL1 DL2
3

B220LFA 1845_DH1 0R3-U

L12 28 16
1 2 CS1 CS2
MAX1845_LX1
MAX1845_DL1
IND-1D4UH 1 15
OUT1 OUT2
1
1

TC15 TC14 2 14
FB1 FB2
8

5
ST150U6D3VDM-5

ST150U6D3VDM-5

R378 D71
2

1
15KR3F SSM34A 11 12
ON1 ON2
2
2

R733 5 7
0R3-U 10 TON PGOOD
REF

2
U83 8
43,46,59 +PWRON OVP
TPC8014-N 6

GND
SKIP#
1

R375 MAX1845EEI-U
1

23
10KR3F 1845_DL1
2

Rds(on) = 22 mohm
MAX1845_VREF

1
R728 D72 C374 C369
1 2 1 2
41,43,53 PM_SLP_S3#

2
1KR2 S1N4148-1-U

SC1U10V3KX

SC33P50V2J
R723
1

1 2 C691
2

470KR2
SCD1U25V3KX

R707 D69
2 1 1 2
38,43,46,55,57,59 B_ON

24
1KR2 S1N4148-1-U

S Note Power Sequence Presentation

 VCC2R5A
+PWRON MAXIM1845 ON1, TSURUMAI 3A_ON U36 Pin 63
VCC2R5A OUT1 of MAXIM 1845 U43 Pin1

25 S Note Power Sequence Presentation

 DDR_VREF
MAXIM8880 SHDN#, LP2996 SD#, MAXIM4245 SHDN#, MAXIM1992
B_ON R350 Pin 2
SHDN#, TSURUMAI 3B_ON, 5B_ON, RD2_ON
VCC2R5A OUT1 of MAXIM 1845 U43 Pin1
DDR_VREF Voltage of DDR SODIMM U7 Pin 4

VCC2R5A DDR_VREF

1
R472 C53

2
100KR2 U7 SCD01U25V2KX

2
D47
B_ON 2 1 LP2996_SD# 2 4 VCC1R25B
VCC2R5A 5 SD# VREF
1SS400 6 VDDQ 3
7 AVIN VSENSE 8
PVIN VTT

GND
GND
1

1
TC1 C493 C490 C484 LP2996MR-U C38 TC12
2

2
ST68U6D3VM-U SC1U10V3KX SCD01U25V2KX SCD01U25V2KX SCD01U25V2KX ST220U4VDM-1

9
1
26 S Note Power Sequence Presentation
 VCC3B & VCC5B & VCCACPU
VCC3B VCC3B power by FDC655AN Q72 Pin 4
VCC5B VCC5B power by FDC655AN Q31 Pin 4
VCCACPU OUT by MAXIM8880 U41 Pin3

VCC3M

U41 VCCACPU

1
1 3
C385 IN OUT

1
SC1U10V3KX
4
FB R354
5 6 402KR3F
43,56 B_ON SHDN# POK

2
GND
C371
MAX8880EUT-T SC4D7U10V-U

1
2
R340
931KR2F

2
R354 VCCACPU
BANIAS 402Kohm 1.80V
DOTHAN 187Kohm 1.50V

27 S Note Power Sequence Presentation

 VCCGMCHCORE & MICVCC & VCCCPUIO

Core power of Motara-GM Plus power by MAXIM 4245

VCC1R5M

MICVCC power by LP4085

1

C329 VL5
SC47U6D3V0ZY
2

MAX1845_VREF
VCC5M MICVCC
BC83

1
Q27 SCD1U16V3ZY U37

1
5 D G 4
6 D S 3 R670 C654 1 5
VIN VOUT
1

2
7 D S 2 U73 49K9R3F SC1U10V5KX 2
GND

2
8 D S 1 43,56 B_ON
3 4
VEN BYPASS
R684 6 1
VDD IN+

1
FDS6680A 1MR2 5 2
SHDN# VSS AGND LP3985IM5X-4D7 C662 C658 C660 C330 C328
2

1
4 3

2
OUT IN- SCD01U25V2KX SCD33U16V3ZY SC1U10V3KX SC2D2U10V5MX-U1 SC2D2U10V5MX-U1
1D35V / 2.2A 1 C652 R668
C661

2
SC1U10V3KX
2
MAX4245AXT-T SC1U10V3KX 105KR3F
VCCGMCHCORE

2
AGND
R675
1 2
1

BC81 SC20P 1K5R3

1

R681
C320 TC13 R678 DUMMY-R2
2

DUMMY-C3 ST150U6D3VM-U 1 2
2

1KR3F

R688
1 2
43,56 B_ON
1

0R3-U

C666
DUMMY-C3

VCCGMCHCORE R670 R668

2

MONTARA GM 1.2V 69.8K Ohm 105K Ohm

MONTARA GM+ 1.35V 49.9K Ohm 105K Ohm

28 S Note Power Sequence Presentation

 VCCGMCHCORE & MICVCC & VCCCPUIO

CPU I/O power by MAXIM 1992

MAX1992_VCC VL5
R461 R489
1 2 1 2
1

1
20R5 0R3-U

1
C497 C519
2

2
SC1U10V3KX SC1U10V3KX D50
BAT54S-U1

3
VINT16 VINT16

1
22

19

1
U59 C521

1
SCD1U50V3KX
54 VTT_PWRG
VCC

VDD

R501 C546

2
B_ON 0R3-U U17 SC4D7U25V-U

2
1
3 14 R129
4 LSAT V+ 17 1 2 8 2
23 PGOOD BST 15 VCCCPUIO
1 SHDN# DH 16 0R3-U 7
MAX1992_REF 13 TON LX 18 R91 L24 R93
SKIP# DL 20 1 2 3 6 1 2 1 2
6 PGND 21
REF AGND

1
5 11 0R3-U 4 5 IND-3D3UH-17 D015R2512F-2
ILIM CSP
1

12 TC3
CSN

2
C487 2 10 SI4814DY ST150U6D3VM-U
NC OUT
2

SCD22U10V3KX R60 7 C125

NC

2
100KR2F 8 SCD1U25V3KX
NC
2

FB
9 For EMI Sanyo TPC 40mR

1
25 24
AGND OVP/UVP R477
1

1 5K11R3F
C63 MAX1992ETG

2
2 SC470P50V2KX R61
42K2R2F
MAX1992_VCC
2

1
R483
10K2R3F

2
29 S Note Power Sequence Presentation
 VCCGMCHCORE & MICVCC & VCCCPUIO
VCCGMCHCORE Core power of Motara-GM Plus TC13 Pin 1
MICVCC VOUT of LP3985 U37 Pin 5
VCCCPUIO CPU I/O power by MAXIM 1992 TC3

30 S Note Power Sequence Presentation

 VCC1R5B & VCC1R5B_DRV
VCC1R5B_DRV RD2_DRV of TSURUMAI U28 Pin 35
VCC1R5B VCC1R5B power by FDC655AN Q28 Pin 4

31 S Note Power Sequence Presentation

 APWRG & BPWRG
APWRG

In the block of A_PGS, the voltage of VCC3A is monitored by the internal analog comparator, each state is supplied to A_PGS output.
The terminal is Open drain structure.

The operation of detection is started when 3A_ON is equal to High. The analog Comparator has hysteresis voltage and generate
highsignal when the following condition are satisfied.

Greater than 2.943V(Typ.) at power on stage of "VCC3A" （ Rising Edge ） and lower than 2.793V (Typ.) at the shut down stage
(Falling edge) In this period A_PGS is supplying H level.

The Hysteresis Voltage are set 150mV +/- 50mV. At the High state, the delay time of 350ms +/- 10ms is set.

32 S Note Power Sequence Presentation

 APWRG & BPWRG
BPWRG

In the block of B_PGS, the voltage of VCC5B and VCC3B are monitored by the internal analog comparator, each voltage state issupplied
to B_PGS output. The terminal is Open drain structure.

The operation of detection is started when both 5B_ON and 3B_ON are equal to High. The analog Comparator has hysteresis

voltage and generate high signal when the following condition are satisfied.

Greater than 4.461V(Typ.) at power on stage of "VCC5M" （ Rising Edge ） and lower than 4.311V (Typ.) at the shut down stage

(Falling edge) after 47.5ms +/- 2.5ms

Greater than 2.943V(Typ.) at power on stage of "VCC3M" （ Rising Edge ） and lower than 2.793V (Typ.) at the shut down stage

(Falling edge) after 47.5ms +/- 2.5ms

In this period B_PGS is supplying H level. The Hysteresis Voltage are set 150mV +/- 50mV.

And at the High state, the delay time is set, when B_PGS become High, the delay time of 100ms +/- 5ms is set in case of A_PGS is equal to
Low, and the delay time of 445ms +/- 5ms is set in case of A_PGS is equal to High.

33 S Note Power Sequence Presentation

 APWRG & BPWRG
BPWRG

34 S Note Power Sequence Presentation

 APWRG & BPWRG
MPWRG Output for VCC3M/VCC5M Power Good Signal (Open-Drain) U28 Pin51
APWRG Output for VCC3A Power Good Signal (Open-Drain) U28 Pin 49
BPWRG Output for VCC5B/VCC3B Power Good Signal (Open-Drain) D30 Pin 1

Spec: From APWRG to BPWRG is 100+/-5ms

35 S Note Power Sequence Presentation

 VTT_PWRG
VTT_PWRG CPU I/O power good U59 Pin 4

36 S Note Power Sequence Presentation

 VCCCPUCORE & VR_PWRGD

VCCCPUCORE & VR_PWRGD by MAXIM 1907

R 53
VC C 5B 1 2
VIN T16
0R 1210
D C BATOU T_MAX1907

2
MAX1907_VC C D C BATOU T_MAX1907
C 50 R 459

1
VC C 3B 1 2 0R 3-U

1
MAX1907_5V C 52 C 51 C 518 C 517 C 516
SC 4D 7U 25V-1-U

2
C 30 R 38 SC D 1U 50V3ZY SC 2K2P SC D 1U 50V5KX SC 4D 7U 25V-1-U SC 4D 7U 25V-1-U
2 1
1

SC 4D 7U 10V5ZY 10R 3
1

5
6
7
8
R 443

D
D
D
D
2
R 450 R 455 100KR 2 U 12 C 71 For EMI recommendation:
10

34
100KR 2 100KR 2 SC 4D 7U 10V5ZY D 45
Place C529 near U59 (5, 6, 7, 8 pin)
2

U 13
MBR 0530T1 Wide and short pattern

V+
2

VC C

30 IR F7811AV
VD D

G
38 R 59

S
S
S
3 C LK_EN ABLE# C LKEN #
36 31 MAX1907_BSTR
1 2 MAX1907_BST
55 VTT_PW R G SYSPOK BST
VR _PW R GD 37
21 VR _PW R GD IMVPOK

4
3
2
1
0R 3-U R 63
MAX1907_S0 4 33 MAX1907_D H C 58 1 2 1907_D H G3
S0 DH

1
MAX1907_S1 5 SC D 1U 0R 3-U 1 2
6 S1 32 MAX1907_LX VC C C PU C OR E_D C VC C C PU C OR E
MAX1907_S2
S2 LX GAP-OPEN
R 128
R N 50 SR N 0-1-U 29 MAX1907_D L L25 G4
5 H _VID [5:0] DL
H _VID 0 1 8 26 1 2 1 2 1 2
2 7 25 D0
H _VID 1
D1

1
H _VID 2 3 6 24 28 R 54 200R 2F IN D -D 8U H -1 D 002R 3264F-L GAP-OPEN
4 5 23 D2 PGN D 1 2
H _VID 3 G5

ST220U 2VD M-1

D3

D 8

D 7

D 6

D 5

D 8

D 7

D 6

D 5

1
H _VID 4 2 3 22 R 120 1 2

ST220U 2VD M-1

H _VID 5 1 4 21 D4 C 485 SC 1000P50V 0R 3-U TC 6 TC 5

ST220U 2VD M-1

D5

2
R N 51 SR N 0-2-U 18 1907_C SP1 C 561 GAP-OPEN
1 C SP 19 1 R 58 2 D 46 SC 1U 10V3KX TC 4
MAX1907_B0 1907_C SN 1 G6
B0 C SN

2
MAX1907_B1 2 200R 2F 1 2
B1 SSM34A

1907_D L
MAX1907_B2 3 U 20 U 15
B2

2
17 MAX1907_OAIN + 1 R 52 2 D Y-IR F7832-U IR F7832-U GAP-OPEN
OAIN + 16 10R 2 G7
OAIN -
VC OR E_ON 7 Droop 1 2
1

SH D N # C 479 SC 470P50V2KX

1 S

2 S

3 S

4 G

1 S

2 S

3 S

4 G
Ton=NC, Freq.=300KHz
MAX1907_TON 40 15
MAX1907_OAIN - 1
R 51
2
1KR 2F
For EMI recommendation GAP-OPEN
G8
TON FB near L22 (2 pin)
1

C 469 C 37 SC 100P50V2J N 1 2
1 2 Wide and short pattern
R 41 1 2 MAX1907_C C 12 GAP-OPEN
D U MMY-R 2 CC 14
SC 270P50V2J X N EG 1 R 46 2
2

10R 2 1907_C SP
8 13 MAX1907_N EG
R EF POS
Offset
9 MAX1907_POS
MAX1907_R EF ILIM
1

11
GN D
D PSLP#

27 41 R 43
D D O# NC
MAX1907_ILIM
1

C 31 R 40 1K05R 3F
SU S

TIME

SC D 22U 10V3KX 180KR 3F

2

MAX1907AETL-U
close to IC active voltage position.
20

35

39

close to IC 1
R 39
2
25A ILIM: 2*91 / (91+180) = 0.671V
OCP: 61.7 / 2 = 33.5A
MAX1907_TIME
1

100KR 2F G1
1

1 2 12A ILIM: 2*39 / (39+180) = 0.356V

R 64 R 50 R 45
OCP: 35.6 / 2 = 17.8A
R 36 0R 2-0 0R 2-0 62KR 3
offset 1.040.% GAP-C LOSE
2

91KR 3D
2

3,21 PM_C PU STP#

21 PM_D PR SLPVR

R583 should be changed to 39Kohm for 12A

37 S Note Power Sequence Presentation

 VCCCPUCORE & VR_PWRGD
VTT_PWRG CPU I/O power good U59 Pin 4
VCORE_ON MAXIM1907 SHDN# U12 Pin 7
VCCCPUCORE CPU Core power TC4, TC5, TC6
VR_PWRGD MAXIM 1992 IMVP OK U12 Pin 37

38 S Note Power Sequence Presentation

 PCIRST# & CC_CPUPWRGD
VR_PWRGD MAXIM 1992 IMVP OK U12 Pin 37
BPWRG(PWROK) Output for VCC5B/VCC3B Power Good Signal (Open-Drain) D30 Pin 1
ICH4 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH4
PCIRST# asserts PCIRST# during power-up and when S/W initiates a hard reset sequence R238 Pin1
through the RC (CF9h) register
This signal should be connected to the processor’s PWRGOOD input. allow for Intel
CC_CPUPWRGD ® SpeedStep™ technology support, this signal is kept high during an Intel SpeedStep R259 Pin 2
technology state transition to prevent loss of processor context.
Spec: From BPWRG to PCIRST# is 1ms

39 S Note Power Sequence Presentation

 GTL_CPURST#
The CPURST# pin is an output from the MGMCH. The MGMCH asserts
GTL_CPURST# CPURST# while RSTIN# (PCIRST# from ICH4) is asserted and for approximately R630 Pin 2
1 ms after RSTIN# is deasserted.

Spec: From PCIRST# to GTL_CPURST# is 1ms

40 S Note Power Sequence Presentation

 GTL_ADS# & LPC_FRAME#
The processor bus owner asserts ADS# to indicate the first of two cycles of a request
GTL_ADS# Test pad
phase.
LPC_FRAME# LFRAME# indicates the start of an LPC cycle, or an abort. U36 Pin 4

41 S Note Power Sequence Presentation

 P_TRDY# & P_IRDY# & P_FRAME#
TRDY# indicates the ICH4's ability, as a Target, to complete the current data phase
P_TRDY# of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is RN41 Pin2
completed when both TRDY# and IRDY# are sampled asserted.
TRDY# indicates the ICH4's ability, as an Initiator, to complete the current data
P_IRDY# phase of the transaction. It is used in conjunction with TRDY#. A data phase is RN41 Pin3
completed on any clock that both IRDY# and TRDY# are sampled asserted.
The current Initiator drives FRAME# to indicate the beginning and duration of a PCI
P_FRAME# transaction. While the Initiator asserts FRAME#, data transfers continue. When the RN41 Pin4
Initiator negates FRAME#, the transaction is in the final data phase.

42 S Note Power Sequence Presentation

 S0 TO S3 This signal will typically be configured as C3_STAT#. It is used for indicating to an
C3_STAT# AGP device that a C3 state transition is beginning or ending. If C3_STAT# NA
functionality is not required, this signal may be used as a GPO.
This signal puts the processor into a state that saves substantial power compared to
CC_CPUSLP# Stop-Grant state. However, during that time, no snoops occur. The ICH4 can Test pad
optionally assert the CPUSLP# signal when going to the S1-M state.
Output to the external clock generator for it to turn off the processor clock. Used to
PM_CPUSTP# support the C3 state. If this functionality is not needed, this signal can be configured as R64 Pin2
a GPO.
This signal is asserted by the ICH4 to indicate that the system will be entering a low
PM_SUS_STAT# power state soon. This can be monitored by devices with memory that need to switch R881 Pin2
from normal refresh to suspend refresh mode. It can also be used by other peripherals
This signal is an output to the external clock generator for it to turn off the PCI clock.
PM_PCISTP# Used to support PCI CLKRUN# protocol. If this functionality is not needed, This U29 Pin34
signal can be configured as a GPO.

43 S Note Power Sequence Presentation

 S0 TO S3 This signal is an output to the external clock generator for it to turn off the PCI clock.
PM_PCISTP# Used to support PCI CLKRUN# protocol. If this functionality is not needed, This U29 Pin34
signal can be configured as a GPO.
SLP_S1# provides Clock Synthesizer or Power plane control. Optional use is to shut
PM_SLP_S1# off power to non-critical systems when in the S1-M (Powered On Suspend), S3 U29 Pin 25
(Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states.
ICH4 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH4
PCIRST# asserts PCIRST# during power-up and when S/W initiates a hard reset sequence R238 Pin1
through the RC (CF9h) register
SLP_S3# is for power plane control. It shuts off power to all non-critical systems
ICH_SLP_S3# Test pad
when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

44 S Note Power Sequence Presentation

 S3 TO S0

45 S Note Power Sequence Presentation

 S3 TO S0

46 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCC1R25B

S0 TO S3 S3 TO S0

47 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCC3B

S0 TO S3 S3 TO S0

48 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCC5B

S0 TO S3 S3 TO S0

49 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCCACPU

S0 TO S3 S3 TO S0

50 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCCCPUIO

S0 TO S3 S3 TO S0

51 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCCGMCHCOR
E

S0 TO S3 S3 TO S0

52 S Note Power Sequence Presentation

 S0 TO S3 & S3 TO S0 POWER STATUS
VCPU CORE ON

S0 TO S3 S3 TO S0

53 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1977

VCC3M

PLUG IN ADT SHUTDOWN THE SYSTEM

54 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1977

VCC5M

PLUG IN ADT SHUTDOWN THE SYSTEM

55 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1845

VCC1R5M

PLUG IN ADT SHUTDOWN THE SYSTEM

56 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1845

VCC2R5A

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

57 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1907

VCCCPUCORE

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

58 S Note Power Sequence Presentation

 PWM POWER ON/OFF STATUS
MAXIM 1992

VCCCPUIO

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

59 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
LP2996

DDR_VREF & VCC1R25B

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

60 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
MAXIM 1935

VCC1R8M

PLUG IN ADT SHUTDOWN THE SYSTEM

61 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
MAXIM 1935

VCCGBECOREAUX

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

62 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
MAXIM 1683

VDD15

PLUG IN ADT SHUTDOWN THE SYSTEM

63 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
TSURUMAI

VCC3SW

PLUG IN ADT PLUG OUT ADT

64 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
MAXIM 8880

VCCACPU

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

65 S Note Power Sequence Presentation

 LDO POWER ON/OFF STATUS
MAXIM 4245

VCCGMCHCORE

PRESS POWER BUTTON ON SHUTDOWN THE SYSTEM

66 S Note Power Sequence Presentation