DIGITAL LOGIC DESIGN LAB

(Course Code: ECE 1003)

EXPERIMENT No.1
Verification of Logic Gates in behavioural,
structural and Dataflow modelling
B NAGA RAJU
APC- SENSE
nagaraju.b@vitap.ac.in
•List of Laboratory Experiments

1. Verification of Basic gates in behavioral, dataflow and gate-level modeling.

2. Verification of half adder & subtractor, full adder and subtractors.
3. Design and verification of 4-bit binary adder and subtractor.
4. Design and verification of 3x8 decoder and 8x3 priority encoder.
5. Design and verification of 4x1 MUX and 1x4 DeMUX.
6. Design and verification of 4-bit magnitude comparator.
7. Verification of latches and flip-flops.
8. Design and verification of 4-bit shift registers – SISO, SIPO, PISO and PIPO
9. Design and verification of 4-bit asynchronous up, down, up/down counter.
10. Design and verification of 4-bit synchronous up, down, up/down counter.
11. Design and verification of 4-bit ring and Johnson counters.
IC Packages Types
 Logic gates
Logic gates are the building block of digital circuit and system. We can make any digital
circuit using logic gates. The are three basic logic gates AND, OR and NOT gate, two universal
gate NAND and NOR and two other special logic gates Ex-OR and EX-NOR

Logic Gates

Basic Logic Gates Universal Gates Special Gates

AND, OR and NOT NAND and NOR Ex-OR and EX-NOR

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 Logic gates
Basic Logic Gates

Gate Logic Symbol Boolean Truth Table

Expression

AND Gate

OR Gate

Not Gate

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 Logic gates
Universal Gates

Gate Logic Symbol Boolean Truth Table

Expression

NAND Gate

NOR Gate

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 Logic gates
Special Gates

Gate Logic Symbol Boolean Truth Table

Expression

Ex-OR Gate

Ex-NOR Gate

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 HDLs (hardware description languages)
A hardware description language (HDL) is a programming language used to describe the
behavior or structure of digital circuits (ICs). HDLs are also used to stimulate the circuit
and check its response. Many HDLs are available, but VHDL and Verilog are by far the
most popular

HLDS

VHDL
(VHSIC) HDL Verilog HDL

Note: VHSIC Stands for Very High Speed Integrated Circuit

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VHDL Program Structure

Heart :Entity and

Architecture

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Verilog Program Structure
Heart :Module

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 AND gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module and_gate_tb;
//AND gate using //AND gate using data //AND gate using reg a,b;
behavioural modeling flow modeling Structural modeling wire y;
module and_gate_b(a,b,y); module and_gate_d(a,b,y); module and_gate_s(a,b,y);and_gate_s uut(a,b,y);
input a,b; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; #10
output y;
b = 0; b = 1;
#10
a = 1; b = 0;
always @ (a,b) #10
assign y = a & b; and(y,a,b);
y = a & b; b = 1; b = 1;
#10
$finish();
endmodule end
endmodule endmodule
endmodule

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 NAND gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module nand_gate_tb;
//NAND gate using //NAND gate using data //NAND gate using reg a,b;
behavioural modeling flow modeling Structural modeling wire y;
module nand_gate_b(a,b,y); module nand_gate_d(a,b,y); module nand_gate_s(a,b,y); nand_gate_s uut(a,b,y);
input a,b; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; output y; #10
b = 0; b = 1;
always @ (a,b) #10
begin a = 1; b = 0;
If (a==0 & b==0)
Y=1; assign y = ~(a & b); nand(y,a,b); #10
Else if(a==0 & b==1) b = 1; b = 1;
Y=1; #10
Else if(a==1 & b==0)
Y=1;
$finish();
Else endmodule endmodule end
Y=0;
//or// endmodule
y = ~(a & b);
endmodule
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 Behavioural
Modeling
#1 #2.
.//NAND gate using behavioural modeling
module nand_gate_b(a,b,y); //NAND gate using
input a,b; behavioural modeling
output y;
module nand_gate_b(a,b,y);
always @ (a,b)
begin input a,b;
if (a==0 & b==0)
y=1; output y;
else if(a==0 & b==1)
y=1;
else if(a==1 & b==0) always @ (a,b)
Y=1;
else y = ~(a & b);
y=0;
endmodule
end
endmodule

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 OR gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module or_gate_tb;
//OR gate using //OR gate using data //OR gate using reg a,b;
behavioural modeling flow modeling Structural modeling wire y;
Module or_gate_b(a,b,y); Modul or_gate_d(a,b,y); Modul or_gate_s(a,b,y); or_gate_s uut(a,b,y);
input a,b; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; #10
output y;
b = 0; b = 1;
#10
a = 1; b = 0;
always @ (a,b) #10
assign y = a | b; or(y,a,b);
y = a | b; b = 1; b = 1;
#10
$finish();
endmodule end
endmodule endmodule
endmodule

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 NOR gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module nor_gate_tb;
//NOR gate using //NOR gate using data flow //NOR gate using Structural reg a,b;
behavioural modeling modeling
modeling
wire y;
module nor_gate_b(a,b,y); module nor_gate_d(a,b,y); module nor_gate_s(a,b,y);nor_gate_s uut(a,b,y);
input a; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; #10
output y;
b = 0; b = 1;
#10
a = 1; b = 0;
always @ (a,b) assign y = ~(a | b); #10
nor(y,a,b);
b = 1; b = 1;
y = ~(a | b); #10
$finish();
endmodule endmodule end
endmodule
endmodule

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 EX-OR gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module xor_gate_tb;
//Ex-OR gate using //Ex_ORgate using data //Ex-OR gate using reg a,b;
behavioural modeling flow modeling Structural modeling wire y;
Module xor_gate_b(a,b,y); module xor_gate_d(a,b,y); module xor_gate_s(a,b,y);xor_gate_s uut(a,b,y);
input a,b; input a,b; initial begin
input a,b;
a = 0; b = 0;
output y; output y; #10
output y;
b = 0; b = 1;
#10
always @ (a,b) a = 1; b = 0;
assign y = (a ^ b); xor(y,a,b); #10
y = (a ^ b); b = 1; b = 1;
#10
endmodule $finish();
endmodule endmodule end
endmodule

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 Ex-NOR gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module xnor_gate_tb;
//EX-NOR gate using //EX-NOR gate using //EX-NOR gate using reg a,b;
behavioural modeling data flow modeling Structural modeling wire y;
modulexnor_gate_b(a,b,y); module xnor_gate_d(a,b,y);module xnor_gate_s(a,b,y);
xnor_gate_s uut(a,b,y);
input a,b; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; output y; #10
b = 0; b = 1;
#10
a = 1; b = 0;
always @ (a,b) #10
assign y = ~(a ^ b); xnor(y,a,b);
b = 1; b = 1;
y = ~(a ^ b); #10
endmodule $finish();
endmodule endmodule end
endmodule

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 Not gate

Behavioural Data Flow Modeling Structural Modeling Test bench

//NOT gate using //NOT gate using data //NOT gate using module not_gate_tb;
behavioural modeling flow modeling Structural modeling reg a;
wire y;
module not_gate_b(a,y); module not_gate_d(a,y); module not_gate_s(a,y);
input a; input a; input a; not_gate_s uut(a,y);

output reg y; output y; output y; initial begin

always @ (a) assign y = ~a; a = 0;
#10
y = ~a; not(y,a); b = 1;
endmodule #10
endmodule endmodule
$finish();
end

endmodule

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module and_s_tb; EDA Playground Testbench
reg a,b;
wire c;

and_s dut(.a(a),.b(b),.c(c));

initial begin
a = 0; b = 0;
#10
a = 0; b = 1;
#10
a = 1; b = 0;
#10
a = 1; b = 1;
#10

$finish();
end
initial begin
$dumpfile("and_s_tb.vcd");
$dumpvars();
end

endmodule

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module and_s_tb;
reg a,b;
EDA Playground Testbench Syntax
wire c;

and_s dut(.a(a),.b(b),.c(c));

initial begin
a = 0; b = 0;
#10
a = 0; b = 1;
#10
initial begin
a = 1; b = 0; $dumpfile("and_s_tb.vcd");
#10 $dumpvars();
a = 1; b = 1; end
#10

$finish();
end
initial begin
$dumpfile("and_s_tb.vcd");
$dumpvars();
end

endmodule

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 AND gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module and_gate_tb;
reg a,b;
Truth <= Gate wire y;
and_gate_s uut(a,b,y);
Table/Behavi Assignment LEVEL initial begin
a = 0; b = 0;
our of
operators CIRCUIT/ #10
b = 0; b = 1;
circuit / #10
a = 1; b = 0;

/ Gates: #10
b = 1; b = 1;
#10
Nand $finish();

Always Assign And

end
endmodule
Or
And a1()

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 NAND gate

Behavioural Data Flow Modeling Structural Modeling Test bench

module nand_gate_tb;
//NAND gate using //NAND gate using data //NAND gate using reg a,b;
behavioural modeling flow modeling Structural modeling wire y;
module nand_gate_b(a,b,y); module nand_gate_d(a,b,y); module nand_gate_s(a,b,y); nand_gate_s uut(a,b,y);
input a,b; input a,b; input a,b; initial begin
a = 0; b = 0;
output y; output y; output y; #10
b = 0; b = 1;
always @ (a,b) #10
begin a = 1; b = 0;
If (a==0 & b==0)
Y=1; assign y = ~(a & b); nand(y,a,b); #10
Else if(a==0 & b==1) b = 1; b = 1;
Y=1; #10
Else if(a==1 & b==0)
Y=1;
$finish();
Else endmodule endmodule end
Y=0;
//or// endmodule
y = ~(a & b);
endmodule
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 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

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