Interrupt

Chapter 10

Sepehr Naimi

www.NicerLand.com
 Contents
 Polling Vs. interrupt
 Interrupt unit
 Steps in executing an interrupt
 Edge trigger Vs. Level trigger in external
interrupts
 Timer interrupt
 Interrupt priority
 Interrupt inside an interrupt
 C programming

2
 Polling Vs. Interrupt
Two methods by which a device receives service from a MCU:
 Interrupt
 Polling  Whenever a device needs the MCU
 MCU monitors the status of the service, it notifies the MCU by
device and performs the service sending an interrupt signal. The
when status condition is met. MCU stops whatever it is doing and
 Ties down the CPU serves the device.
 Efficient CPU use
while (true)
 Has priority
{  Can be masked
if(PIND.2 == 0) main( )
//do something; {
} Do your common task
}
whenever PIND.2 is 0 then
do something
3
 Interrupt Controllers

Peripherals
Timers
IRQ0
CPU IRQ1 I/Os
Interrupt IRQ2
Controller IRQ3 USART

….
IRQn
SPI

4
 Interrupt control unit in AVR

SREG I T HRAM S V EEPROM

N Z C Timers
PROGRAM
ROM

Program
Bus Bus
CPU

SREG

EIMSK
PCICR
PCMSK0
PCMSK1 Other
OSC PCMSK2 Ports
Peripherals
Interrupt Unit
TIMSK0
TIMSK1
TIMSK2
I/O
PINS

5
 Interrupt vectors in ATmega328
 Interrupt vector
Interrupt Address
table (hex)
Reset 0000
External Interrupt Request 0 0002
External Interrupt Request 1 0004
Pin Change Interrupt Request 0006
Pin Change Interrupt Request 0008
Pin Change Interrupt Request 000A
Watchdog Time-out Interrupt 000C
Timer/Counter2 Compare Match A 000E
Timer/Counter2 Compare Match B 0010
Timer/Counter2 Overflow 0012
Timer/Counter1 Capture Event 0014
Timer/Counter1 Compare Match A 0016
Timer/Counter1 Compare Match B 0018
Timer/Counter1 Overflow 001A
Timer/Counter0 Compare Match A 001C
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 Interrupt execution steps
 The MCU finishes the instruction it is currently executing and
saves the address of the next instruction (PC) on the stack
 It jumps to a fixed location in memory called “interrupt vector
table”, which directs the MCU to the address of the interrupt
service routine (ISR).
 The MCU starts to execute the ISR until it reaches the last
instruction of the subroutine, which is the RETI (return from
interrupt)
 The MCU returns to the place where it was interrupted: first it
gets the PC address from the stack by popping the top byte of
the stack into the PC, then it starts to execute from that addr.

7
 Interrupt sources in AVR
 At least 2 interrupts for each timer (overflow and compare
match).
 Three external hardware interrupts. In atmega32, Pins PD2,
PD3 and PB2 are for external hardware interrupts INT0, INT1,
and INT2 respectively.
 3 interrupt for Serial communication’s USART: one for receive
and two for transmit (to cover in ChP11)
 SPI interrupts (Chp17)
 ADC  Chp 13

8
 Steps in enabling an interrupt
 Bit D7 (I) of the SREG register set to high to allow interrupts.
 This is done with the SEI (set interrupt) instruction or macro (for C)
 If I=1, each interrupt is enabled by setting to HIGH the
interrupt enable (IE) flag bit for that interrupt.
 TIMSK register holds the interrupt enable bits for Timer0,1 and 2.
 If I=0, no interrupt will be responded to, even if its IE bit is high.

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Timer interrupt Mask

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 Review Questions
1. Of the interrupt and polling methods, which one avoids tying
down the MCU?
2. Give the name of the interrupts in the TIMSK register.
3. Upon power-on reset of the ATmega32, what memory area is
assigned to the interrupt vector table? Can the programmer
change the memory space assigned to the table?
4. What is the content of D7 (I) of the SREG register upon
reset, and what does it mean?
5. What address in the interrupt vector table is assigned to
Timer1 overflow and INT0 interrupts?

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 Review Questions- answer
1. Of the interrupt and polling methods, which one avoids tying
down the MCU? interrupts
2. Give the name of the interrupts in the TIMSK register.
Timer0 overflow, Timer0 compare match, Timer1
overflow, Timer1 compare match, Timer2 overflow,
Timer2 compare match,
3. Upon power-on reset of the ATmega32, what memory area is
assigned to the interrupt vector table? 0x00 to 0x28, Can
the programmer change the memory space assigned to the
table? No, it is set when the processor is designed
4. What is the content of D7 (I) of the SREG register upon
reset, and what does it mean? I=0, meaning that all
interrupts are masked (no interrupt will be responded
to by AVR)
5. What address in the interrupt vector table is assigned to
Timer1 overflow and INT0 interrupts? 0x12 (for Timer1
overflow) and 0x02 for INT0
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External Interrupts

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External Interrupts (ATmega328)
D7 D0
EIMSK: - - - - - - INT1 INT0

28 pin
(PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0 2 27 PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1 3 26 PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2 4 MEGA328 25 PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3 5 24 PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4 6 23 PC0 (ADC0/PCINT8)
VCC 7 22 GND
GND 8 21 AREF
(PCINT6/XTAL1/TOSC1) PB6 9 20 AVCC
(PCINT7/XTAL2/TOSC2) PB7 10 19 PB5 (SCK/PCINT5)
(PCINT21/OC0B) PD5 11 18 PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6 12 17 PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7 13 16 PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0 14 15 PB1 (OC1A/PCINT1)

Edge/level
PD2(INT0)
detector
EIMSK.INT0 PC=0x0002

I bit of SREG
EICRA.ISC0x
14
External Interrupts (ATmega32)

15
 Edge trigger Vs. Level trigger in external interrupts

Bit D7 D0

- - - - ISC11 ISC10 ISC01 ISC00

EICRA (Atmega 328) or INT1 INT0

MCUCR (ATmega32)

ISCx1 ISCx0

0 0

0 1

1 0

1 1

EICRA = 0x02; //INT0 on falling edges (Atmega328).

MCUCR = 0x02; //INT0 on falling edges (Atmega32)

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 Review Questions (ext int)
1. True or false. Upon reset, the external hardware INT0-INT2
are edge triggered.
2. For Atmega32, what pins are assigned to INT0-INT2?
3. Show how to enable the INT1 interrupt.
4. Assume that the external hardware interrupt INT0 is
enabled, and is set to the low-edge trigger. Explain how
this interrupt works when it is activated.
5. True or false. Upon reset, the INT2 interrupt is falling edge
triggered.
6. Assume that INT0 is falling edge triggered. How do we
make sure that a single interrupt is not recognised as
multiple interrupts?

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Review Questions-answers (ext int)
1. True or false. Upon reset, the external hardware INT0-
INT2 are edge triggered (only INT2 is).
2. For Atmega32, what pins are assigned to INT0-INT2?
• Bits PD2, PD3, and PB2 are assigned to INT0-2.
3. Set the INT1 bit of GICR register (in addition to the I-
bit)
4. Upon application of a high to low pulse to pin PD2, the
INTF0 flag will be set; as a result, the AVR is
interrupted in whatever is doing, clears the INTF0 flag,
and jumps to ROM location 0x02 to execute the ISR.
5. True
6. When the CPU jumps to the interrupt vector to execute
the ISR, it clears the flag that has caused the interrupt
(INTF0). The INTF0 flag will be set only if a new high-to
low pulse is applied to the pin.
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Program Priority

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 Interrupts priority
What happens when two interrupts are activated at the same
time?
•If 2 interrupts are activated at the same time, the one with the
highest priority is served first.
•The interrupt that has a lower address in the interrupt vector
has a higher priority.
• For instance external interrupt 0 has a higher priority
than ext interrupt 2.

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 Interrupts inside an interrupt
What happens if the AVR is executing an ISR belonging to an
interrupt and another interrupt is activated?

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 Interrupts inside an interrupt
What happens if the AVR is executing an ISR belonging to an
interrupt and another interrupt is activated?
•When the AVR begins to execute an ISR, it disables the I bit of
the SREG register, causing all the interrupts to be disabled, and
no other interrupt occurs while serving the interrupt.
•When the RETI instruction is executed, the AVR enables the I
bit causing the other interrupts to be served.
•If you want another interrupt (any priority) to be served while the
current interrupt is being served, you can set the I bit using the
SEI instruction.
•Do that with care as it may lead to undesirable results (overflow
of stack….)

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 Interrupts latency
The time from the moment an interrupt is activated to the
moment the CPU starts to execute the task is called “interrupt
latency”.
•During this time the PC register is pushed on the stack and
the I bit of the SREG register clears (causing interrupts to be
disabled)
•Its duration can be affected by the type of instruction the CPU
is executing when the interrupt comes in.
•Can last 2 or 4 machine cycles (see datasheet)

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 Review Questions (int priority)
• True or false. In Atmega 32, if the Timer1 and Timer0
interrupts are activated at the same time, the Timer0
interrupt is served first.
• What happens if two interrupts are activated at the same
time?
• What happens if an interrupt is activated while the CPU is
serving another interrupt?
• What factor affect the interrupt latency.

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Review Questions-answers (int priority)
• False. As denoted in the vector table, the address of Timer0
overflow interrupt is 0x16, while that of Timer1 overflow is
0x12.
• The interrupt whose vector is first in the interrupt vector, is
served first.
• The flag of the interrupt will be set, but since I=0, the new
interrupt will not be served. The last instruction of the old
interrupt is REIT, which causes the I falg to be set and the
new interrupt to be served.
• The type of instruction the CPU is executing when the
interrupt comes in.

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Program interrupts in C

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 Program interrupts in C
In WinAVR C language, the following have been added to
manage the interrupts:
1.Interrupt include file: we should include the interrupt header
file (#include <avr/interrupt.h>) if we want to use
interrupts in our program.
2.cli() and sei(): In WinAVR, the cli() and sei() macros are
used to clear and set the I bit of the SREG register.
3.Defining ISR: To write an ISR for an interrupt we use the
following structure (where the interrupt vector name is as
defined in datasheet):

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Program interrupts in C

28
Program interrupts in C (example1)

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Program interrupts in C (example1)

30
Program interrupts in C (example2)

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Program interrupts in C (example1)

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 External Interrupt Sample Code
 Write a program that whenever INT0 goes low, it
toggles PB5 once.

1 .ORG 0 ;location for reset 18 EX0_ISR:

2 JMP MAIN 19 IN R21,PORTB
3 .ORG 0x02 ;loc. for external INT0 20 LDI R22,(1<<5) ;for toggling PB5
4
INT0 21
JMP EX0_ISR EOR R21,R22
5 MAIN: ISR 22 OUT PORTB,R21
6 LDI R20,HIGH(RAMEND) 23 RETI
7 OUT SPH,R20 24
8 LDI R20,LOW(RAMEND) 25
9 OUT SPL,R20 ;initialize stack
10 LDI R20,0x2 ;make INT0 falling
11 STS EICRA,R20
12 SBI DDRB,5 ;PORTB.5 = output
13 SBI PORTD,2 ;pull-up activated
14 LDI R20,1<<INT0 ;enable INT0
Ex. INT0.
15 OUT EIMSK,R20
16 SEI ;enable interrupts
enable
17 HERE:JMP HERE

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 Steps in executing an interrupt
PC6 1 28 PC5
Code
PD0 2 27 PC4
Address .ORG 0
26 PC3
PD1 3 0000 JMP MAIN
(INT0) PD2 4 25 PC2 0002 .ORG 0x02

(INT1) PD3 0002 24 PC1 0002 JMP EX0_ISR

5
23 PC0 0004 MAIN: LDI R20,HIGH(RAMEND)
PD4 6 0005 OUT SPH,R20
VCC 7 22 GND 0006 LDI R20,LOW(RAMEND)
GND 8
ATmega328 21 PB7 0007 OUT SPL,R20

PB6 20 AVCC 0008 LDI R20,0x2 ;make INT0 falling

9
0009 STS EICRA,R20
19 PB5
PB7 10 PC: 0016
0015
0014
0013
0012
000D
0009
000A
000B
000C
0006
0008
000F
0004
000E
0007
0005
0000
PB4
000A SBI PORTD,2 ;pull-up activated
PD5 11 18 000B LDI R20,1<<INT0 ;enable INT0
PD6 12 17 PB3 000C OUT EIMSK,R20

PD7 16 PB2 000D SEI ;enable interrupts

13
000E SBI DDRB,5 ;PORTB.5 = output
PB0 15 PB1
14 000F HERE: INC R25
0010 JMP HERE
EX0_ISR:
0012 IN R21,PORTB
SP 0013 LDI R22,(1<<5) ;for toggling PB5
0014 EOR R21,R22
0015 OUT PORTB,R21
0016 RETI

Stack

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Timer Interrupts

35
 Timer Interrupts

- - - - - OCF0B OCF0A TOV0 TIFR0

D7 D0
TIMSK0: - - - - - OCIE0B OCIE0A TOI0E

- - ICF1 - - OCF1B OCF1A TOV1 TIFR1

D7 D0
TIMSK1: - - ICIE - - OCIE1B OCIE1A TOI1E

- - - - - OCF2B OCF2A TOV2 TIFR2

D7 D0
TIMSK2: - - - - - OCIE2B OCIE2A TOI2E

TOV0
TOIE0 PC=0x0020

I bit of SREG

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 Using Timer0 overflow interrupt
ATmega328
 This program uses Timer0 to generate a square +5

wave on pin PORTB.5, while at the same time PORTB.5

data is being transferred from PORTC to PORTD. PORTD PORTC

1 .ORG 0x0 ;location for reset 19 SBI DDRB,5 ;PB5 as an output

2 JMP MAIN 20 LDI R20,0x00
3 .ORG 0x20 ;location for Timer0 ov. 21 OUT DDRC,R20 ;make PORTC input
4 JMP T0_OV_ISR ;jump to ISR for T0 22 LDI R20,0xFF
5 ;-main program for initialization 23 OUT PORTC,R20 ;enable pull-up
6 MAIN: LDI R20,HIGH(RAMEND) 24 OUT DDRD,R20 ;make PORTD output
7 OUT SPH,R20 25 HERE:IN R20,PINC ;read from PORTC
8 LDI R20,LOW(RAMEND) 26 OUT PORTD,R20 ;give it to PORTD
9 OUT SPL,R20 ;initialize stack 27 JMP HERE
10 LDI R20,-32 ;value for 2 us 28 T0_OV_ISR:
11 OUT TCNT0,R20 ;load Timer0 Timer029 IN R16,PORTB ;read PORTB
12 LDI R20,0x00 ISR 30 LDI R17,(1<<5) ;for toggling PB5
13 OUT TCCR0A,R20 Timer
31 Init.
EOR R16,R17
14 LDI R20,0x01 32 OUT PORTB,R16 ;toggle PB5
15 OUT TCCR0B,R20 ;Normal, no scaler 33 LDI R16,-32 ;timer value for 2 us
16 LDI R20,(1<<TOIE0) 34 OUT TCNT0,R16;load Timer0 with -32
17 STS TIMSK0,R20 ;enable Timer0 Ov. 35Timer Int. ;return from interrupt
RETI
18 SEI ;set I (enable Ints) enable
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 Timer0 Compare Match Interrupt
 using Timer0 and CTC mode generate a square wave on pin PORTB.5, while at the
same time data is being transferred from PORTC to PORTD.
.ORG 0x0 ;location for reset
JMP MAIN
.ORG 0x1C ;ISR location for Timer0 compare match A
JMP T0_CM_ISR
;main program
MAIN:
LDI R20,HIGH(RAMEND)
OUT SPH,R20
LDI R20,LOW(RAMEND) Time (µs)
OUT SPL,R20;set up stack
SBI DDRB,5;PB5 as an output ;--------------- Infinite loop
LDI R20,239 HERE:
OUT OCR0A,R20 ;load Timer0 with 239 IN R20,PINC ;read from PORTC
LDI R20,(1<<WGM01) OUT PORTD,R20 ;and send it to PORTD
OUT TCCR0A,R20 JMP HERE
LDI R20,0x01 ;--ISR for Timer0 (executed every 40 µs)
OUT TCCR0B,R20 ;start Timer0, CTC mode, no scaler T0_CM_ISR:
LDI R20,(1<<OCIE0A) IN R16,PORTB ;read PORTB
STS TIMSK0,R20 ;enable Timer0 compare match interrupt LDI R17,1<<5 ;00100000 for toggling PB5
SEI ;set I (enable interrupts globally) EOR R16,R17
LDI R20,0x00 OUT PORTB,R16 ;toggle PB5
OUT DDRC,R20 ;make PORTC input RETI ;return from interrupt
LDI R20,0xFF
OUT DDRD,R20 ;make PORTD output

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 Interrupt priority
Interrupt Address (hex)
Reset 0000
External Interrupt Request 0 0002 Highest
External Interrupt Request 1 0004 priority
Pin Change Interrupt Request 0006
Pin Change Interrupt Request 0008
Pin Change Interrupt Request 000A
Watchdog Time-out Interrupt 000C
Timer/Counter2 Compare Match A 000E
Timer/Counter2 Compare Match B 0010
Timer/Counter2 Overflow 0012
Timer/Counter1 Capture Event 0014
Timer/Counter1 Compare Match A 0016
Timer/Counter1 Compare Match B 0018
Timer/Counter1 Overflow 001A
Timer/Counter0 Compare Match A 001C
Timer/Counter0 Compare Match B 001E
Timer/Counter0 Overflow 0020
SPI Serial Transfer Complete 0022
USART Rx Complete 0024
USART Data Register Empty 0026 Lowest
USART Tx Complete 0028 priority
ADC Conversion Complete 002A
EEPROM ready 002C
Analog Comparator 002E 39
 Interrupt inside an interrupt
 The I flag is cleared when the AVR begins
to execute an ISR. So, interrupts are
disabled.
 The I flag is set when RETI is executed.

40
 C programming
 Using Timer0 generate a square wave on pin PORTB.5,Vector
Interrupt while at the
Name
same time transferring data External
from PORTC to PORTD.
Interrupt Request 0 INT0_vect
External Interrupt Request 1 INT1_vect
#include "avr/io.h"
Pin Change Interrupt Request PCINT0_vect
#include "avr/interrupt.h"
int main () Pin Change Interrupt Request PCINT1_vect

{ Pin Change Interrupt Request PCINT2_vect

DDRB |= (1<<5); //DDRB.5 = output
Watchdog Time-out Interrupt WDT_vect
TCNT0 = -32; //timerTimer/Counter2
value for Compare
2 µs Match A TIMER2_COMPA_vect
TCCR0A = 0x00; Timer/Counter2 Compare Match B TIMER2_COMPB_vect
TCCR0B = 0x01; //Normal mode,
Timer/Counter2 Overflow
int clk, no prescaler
TIMER2_OVF_vect
TIMSK0 = (1<<TOIE0); //enable
sei ( ); Timer0
//set overflow
I interrupt
Timer/Counter1 Capture Event TIMER1_CAPT_vect
sei (); //enable
cli ( ); interrupts
//clear I
Timer/Counter1 Compare Match A TIMER1_COMPA_vect
DDRC = 0x00; //make PORTC input
DDRD = 0xFF; Timer/Counter1
//make PORTD Compare Match B
output TIMER1_COMPB_vect
while (1) //wait Timer/Counter1
here Overflow TIMER1_OVF_vect
PORTD = PINC; Timer/Counter0 Compare Match A TIMER0_COMPA_vect
} Timer/Counter0 Compare Match B TIMER0_COMPB_vect
ISR (TIMER0_OVF_vect) //ISR for Timer0 overflow
Timer/Counter0 Overflow TIMER0_OVF_vect
{
SPI Serial Transfer Complete SPI_STC_vect
TCNT0 = -32;
USART Rx Complete USART_RX_vect
PORTB ^= 0x20; //toggle PORTB.5
} USART Data Register Empty USART_UDRE_vect
USART Tx Complete USART_TX_vect 41
 C programming Example 2
 Using Timer1 and CTC mode write a program that toggles pin
PORTB.5 every second, while at the same time transferring data
from PORTC to PORTD. Assume XTAL = 16 MHz.
#include <avr/io.h>
#include <avr/interrupt.h>
int main () {
DDRB |= (1<<5); //make DDRB.5 output

OCR1A = 15624;
TCCR1A = 0x00; //CTC mode, internal clk, prescaler=1024
TCCR1B = 0x0D;
TIMSK1 = (1<<OCIE1A); //enable Timer1 compare match A int.
sei (); //enable interrupts

DDRC = 0x00; //make PORTC input

DDRD = 0xFF; //make PORTD output
while (1) //wait here
PORTD = PINC;
}
ISR (TIMER1_COMPA_vect) { //ISR for Timer1 compare match A
PORTB ^= (1<<5); //toggle PORTB.5
}
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 C programming Example 3
 Assume that the INT0 pin is connected to a switch that is normally
high. Write a program that toggles PORTB.5, whenever INT0 pin
goes low.
#include <avr/io.h>
#include <avr/interrupt.h>
int main ()
{
DDRB = 1<<5; //PB5 as an output
PORTD = 1<<2; //pull-up activated
EICRA = 0x2; //make INT0 falling edge triggered

EIMSK = (1<<INT0); //enable external interrupt 0

sei (); //enable interrupts

while (1); //wait here

}

ISR (INT0_vect) //ISR for external interrupt 0

{
PORTB ^= (1<<5); //toggle PORTB.5
}

43