MODULE 5

•Pipelining: An Overview of pipelining, Pipeline

dependencies, Hazards in pipelined processors:
Structural, Data and Control.

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PRESIDENCY UNIVERISTY, BENGALURU, School of Engineering

Computer Organization and Architecture

CSE 2009

Module-4: Part C- Pipelining

Monday, July 22, 2024 2

 AGENDA
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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• To improve the performance of a CPU we have two
options:
1) Improve the hardware by introducing faster circuits.
2) Arrange the hardware such that more than one
operation can be performed at the same time.
• Since, there is a limit on the speed of hardware and the
cost of faster circuits is quite high, we have to adopt the
2nd option.
• Pipelining : Pipelining is a process of arrangement of
hardware elements of the CPU such that its overall
performance is increased. Simultaneous execution of
more than one instruction takes place in a pipelined
processor.
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 What is Pipelining?
• “It is a implementation technique where multiple
tasks are performed in overlapped manner”

• Simple Model
– Instruction Fetch
F1 D1 E1
– Instruction Decode
F2 D2 E2
– Instruction Execute
F3 D3 E3

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 When Can it be implemented?
• It can be implemented when a task can be divided
into two or more subtasks, which can be
performed independently

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ANALOGY

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The same principles apply to processors where we
pipeline instruction execution
• It is classified into five steps:
1. Fetch the instruction from memory.
2. Read registers while decoding the instruction.
3. Execute the instruction.
4. Access an operand in data memory.
5. Write the result into register.

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 Stages for an Unpipelined
Machine
• Every instruction can be executed in 5 steps:

1. IF – Instruction Fetch
– IR Mem[PC]
– NPC  PC + 4 ; Next Program Counter
2. ID – Instruction Decode / Register Fetch
3. EX - Execution / Effective Address Cycle
4. MEM – Memory Access / Branch Completion
5. WB – Write Back
– Writes data back to the REGISTER FILE
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 ADDING PIPELINING
• Run each stage concurrently

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 Pipeline Speed-up
• If the stages are perfectly balanced, then the time
between instructions on the pipelined processor,
assuming ideal conditions is equal to

• Under ideal conditions and with a large number of

instructions, the speed-up from pipelining is
approximately equal to the number of pipe stages; a five-
stage pipeline should be nearly five times faster.
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 But, Remember…

• Pipelining improves performance by increasing

instruction throughput, as opposed to decreasing
the execution time of an individual instruction.

• Instruction throughput is the important metric

because real programs execute billions of
instructions.

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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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 PIPELINE DEPENDENCES
• “Determining how one instruction depends on
another is critical”
Three Types of Dependences:
1. Data Dependences.
2. Name Dependences.
3. Control Dependences.

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 DATA DEPENDENCES
• An instruction ‘j’ is data dependent on instruction
‘i’ iff
– Instruction ‘i’ produces a result that is used by
instruction ‘j’
– Example:
(Instruction i) r3 = r1 + r2
(Instruction j) r5 = r3 + r4

If two instructions are data dependent, they cannot be

executed simultaneously

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 NAME DEPENDENCES
• “Name Dependence will occur when two instructions use the
same register or memory locations, called a name, but there is no
flow of data between the instructions associated with that name.”
– Example:

A= B+ C (Instruction i)

A= P+ Q (Instruction j)

 Original ordering must be preserved to ensure that

finally written value corresponds to ‘j’
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 CONTROL DEPENDENCE
• “Control dependences determines the ordering of
an instruction with respect to a branch instruction:”
– Example
if P1 {
S1;
}
if P2 {
S2;
};
• S1 is control dependent on P1
• S2 is control dependent on P2, but not on P1

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 CONTROL DEPENDENCE
• Two constraints imposed by Control dependences:
1. An instruction that is control dependent on a branch cannot be moved
before the branch.
Ex: We cannot take a instruction from the THEN portion of an IF statement and move it
before IF statement.

2. An instruction that is not control dependent on a branch cannot be moved

after the branch so that its execution is controlled by the branch.

Ex: We cannot take an instruction before the IF and move it into the THEN portion.
When program order is strictly preserved it ensures that control dependences
are also preserved

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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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 Pipelining Hazards
• “Hazards are circumstances that prevent the next
instruction in the instruction stream from executing
during the designated clock cycle”
• There are 3 classes of Hazards:
1. Structural Hazard
Not enough hardware resources to keep all instructions moving.
2. Data Hazard
Data results of the earlier instructions are not available yet
3. Control Hazard
Control decisions resulting from earlier instructions not
yet made; don’t know which new instructions to execute.

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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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STRUCTURAL HAZARD

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 STRUCTURAL HAZARD
• “Structural Hazard arises when there are not
enough hardware resources to keep all instruction
moving.”
• The Structural Hazard occurs when two or more
instructions need the same resource.
• In the above example, the LOAD instruction uses
the memory for a data access at the same time
instruction 3 wants to fetch an instruction from
memory.

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The Structural Hazard causes pipeline
bubbles to be inserted

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 STRUCTURAL HAZARD
• The effect is that no instruction will finish during
clock cycle 8, where instruction 3 would have
normally finished.
• From the above figure we say that, a pipeline is
stalled for a structural hazard when both
instruction and data share the same memory.

• Solution: Split cache like in RISC machines.

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Alternate Depiction of Stall

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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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 DATA HAZARDS
• “Data hazards is created whenever there is a
dependence between the instructions and they are
close enough that the overlap caused by pipelining
would change the order of access to an operand.”
• Example:
– ADD R1, R2, R3
– SUB R4, R1, R5
– AND R6, R1, R7
– OR R8, R1, R9
– XOR R10, R1, R11

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Data Hazard Example

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 DATA HAZARDS
• For the fourth instruction hazard wont occur as we use the concept
of SPLIT PHASE
• In the first half of CC5, data is written (WB is completed for
instruction1) and in the next half of CC5, data is read from the fifth
instruction and correct data is fetched for the sixth instruction as
well

• Solution: Forwarding/Bypassing
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 Road Map
• Overview of pipelining
• Pipeline dependencies
• Hazards in Pipelined processors
– Structural Hazard
– Data Hazard
– Control Hazard

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 CONTROL HAZARDS
• Control hazards result when a branch causes to transfer control to a new
location in the program.
• Control Hazard occur due to instructions changing the PC.

• The simple method of dealing with branches is to STALL the pipeline as soon
as we detect the branch until we reach the MEM stage which determines the
new PC

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 CONTROL HAZARDS

Fig: A branch causes a three cycle stall in the pipeline. One cycle is repeated
(IF cycle) and two cycles are idle.
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 END of Module 4 Part C: Pipelining

3 Monday, July 22, 2024

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