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CG2900

Anton Lee Dec/16/2011

A table of contents
Overview of CG2900 Block diagram Hardware overview Software overview Connectivity interface
1. 2. 3. UART SPI I2C

Question

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5/5/2012

CG2900

GPS Features

1. HCI commands to control all subsystems


2. System interface: UART, SPI, PCM, I2C, MIPI, SLIMbus, GPIO, FM analog audio output, WLAN and WiMAX ePTA 3. Exceeds 3GPP and TIA performance requirements

4. -163 dBm low sensitivity limit for tracking (GPS), -161 dBm for acquisition(aGPS)

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CG2900 Block diagram

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Mobile Phone Hardware overview

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Software overview

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UART(Universal Asynchronous Receive/Transmitter) Interface


Feature
1-bit start generation 8-bit character size

1-bite stop generation


No parity generation and detection Programmable standard baud rates from 38.4kBaud to 1.8432 Mbaud + additional baud rates for fast data transfer from 2.5 Mbaud up to 4.92 MBaud. Automatic line error checking: stop bit failure (framing), RX overrun and break RTS/CTS hardware handshake RXD edge detect

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5/5/2012

UART(Universal Asynchronous Receive/Transmitter)


Interface
Operation

4 wire
1. TxD_UART to transmit the data 2. RxD_UART to receive the data 3. CTS_UART to indicate receive is ready 4. RTS_UART to indicate transmitter is ready

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5/5/2012

UART Resister
Line Status Rgister (LSR)

Interrupt Enable Register

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SPI(Serial Peripheral Interconnect) Interface

Full duplex 8/16/32-bit shift register for Tx/Rx 8-bit Prescaler logic Support 8-bit/16-bit/32-bit bus interface Master-mode and Slave mode Tx/Rx maximum frequency at up to 50Mhz synchronous serial interface used for the GPS/BT/FM

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SPI(Serial Peripheral Interconnect) Interface


5 wires + 1 optional wire
1. CS_SPI to select the device before data exchange 2. CLK_SPI to clock the data

3. MOSI_SPI to receive the data


4. MISO_SPI to transmit the data 5. INT_SPI to indicate a data transmission request 6. FLOW_SPI to control the incoming data flow (optional)

SPI command words

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Operation

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I2C(Inter-Integrated Circuit) Interface


Synchronous serial interface used for efficient inter-IC data exchange in master or slave mode with standard and fast data rate capailities. 2 wires
1. SCL_I2C to clock the data 2. SDA_I2C to receive/transmit the data

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Question

THANK YOU

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