PIC 16C5x

Architecture

Architecture
RISC Processor Harvard Architecture
Separate Buses for Program and Data Instruction size and Data size can be different

CPU
8-bit CPU

CPU
8-bit CPU Dual Pipeline (Fetch and Execute) 12-bit Instruction Register 8-bit General Purpose ALU On Register File and Working Register 8-bit Working Register STATUS Register 2 level deep H/W Stack 33 single word instructions Single cycle instructions except program branches (two cycle) Operating freq. DC-4MHz

Internal Timing
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

PC
CLKOUT

PC+1

PC+2

PC+3

Fetch

Exec

Internal Timing
Instruction Cycle
Q1, Q2, Q3 and Q4 Fetch in one cycle Decode and Execute in the following Cycle

PC is incremented in Q1 and Fetch Execute in the following Cycle Q1-Q4 Data Memory Read in Q2 Data Memory Write in Q4

Memory
Program Memory - Internal Data Memory Internal Program Memory
512 Bytes 2K >512, then by paging 9-bit PC Address wraparound Reset Vector 1FFH NOP @ 1FFH -> restart @ 0000h

Data Memory
Internal Register file General Purpose & SFR Directly or Indirectly accessible by the CPU 25 73 Bytes 7 or 8 Bytes SFR 25 or 24 general purpose registers Special Function Registers Core Peripheral

PIC 16C5x Devices

PIC16C54/55/56/57/58 Difference in
No. of Pins IO EPROM or ROM RAM

Oscillator Selection Options Voltage Range MCLR Filter

Nomenclature
PIC16xx5X: xx Stands for C: EPROM + Std. Op. Voltage LC: EPROM+ Ext. Op. Voltage CR: ROM + Std. Op. Voltage LCR: ROM+ Ext. Op. Voltage UV Erasable in CERDIP Package OTP One Time Programmable QTP Quick Turnaround Production SQTP Serialized QTP

PIC 16C5x Family Devices

Features
Maximum Operating Frequency EPROM Program Memory ( x 12 words) ROM Program Memory ( x 12 words) RAM Data Memory (bytes) Timer Modules IO Pins No. of Instructions

PIC16C54
40MHz 512 25 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

PIC16CR54
20MHz 512 25 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

PIC16C55
40MHz 512 24 TMR0 20 33 28-pin DIP SOIC; 28-pin SSOP

PIC16C56
40MHz 1K 25 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

PIC16CR56
20MHz 1K 25 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

Packages

PIC 16C5x Family Devices

Features
Maximum Operating Frequency EPROM Program Memory ( x 12 words) ROM Program Memory ( x 12 words) RAM Data Memory (bytes) Timer Modules IO Pins No. of Instructions

PIC16C57
40MHz 2K 72 TMR0 20 33 28-pin DIP SOIC; 28-pin SSOP

PIC16CR57
20MHz 2K 72 TMR0 20 33 28-pin DIP SOIC; 28-pin SSOP

PIC16C58
40MHz 2K 73 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

PIC16CR58
20MHz 1K 2K 73 TMR0 12 33 18-pin DIP SOIC; 20-pin SSOP

Packages

Oscillator Options
RC Resistor/Capacitor XT Standard Crystal/Resonator HS High Speed Crystal/Resonator LP Power Saving Low Frequency Crystal

Reset Options
Power On Reset (POR) /MCLR reset (Normal Operation) /MCLR wake-up reset ( from SLEEP) WDT reset ( Normal Operation) WDT wake-up Reset (From SLEEP)

Peripherals
8-bit Timer/Counter with 8-bit Prescalar Power On Reset Device Reset Timer (DRT) Watch Dog Timer Code Protection SLEEP Mode

Ports
RA 4 Bits RB 8 Bits RC 8 Bits Additional Pins
CLKIN CLKOUT /MCLR/Vpp T0CKI

Application of PIC
Applications requiring
Small Size High Speed Low Power IO Flexibility

Application Areas
Automation Motor Control Remote Transmitter/Receiver

STATUS
Address 03H 7 PA2 6 PA1 5 PA0 4 /TO 3 /PD 2 /Z 1 /DC 0 C

PD Time out 0 SLEEP 1 After power u p by CLRWDT TO Time out 0 WDT Time out 1 After power u p by CLRWDT/SLEEP

OPTION
Address 7 6 5 T0CS 4 T0SE 3 PSA 2 PS2 1 PS1 0 PS0

Timer0 CLK Edge Select Timer0 CLK Source 1 = TOCKI pin 0 = CLKOUT 1= at TOCKI pin 0= at TOCKI pin

OPTION
Address 7 6 5 T0CS 4 TOSE 3 PSA 2 PS2 1 PS1 0 PS0

Prescalar Assignment Bit 1 = Prescalar to WDT 0 = Prescalar to Timer0

OPTION
Address 7 6 5 T0CS 4 TOSE 3 PSA 2 PS2 1 PS1 0 PS0

Prescalar Rate Select Bits

Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128

IO Ports
Port A at 05H
4 bit I/O Register

Port B at 06H
8 bit I/O Register

Port C at 07H
8 bit I/O Register for 16C55, 16C57 and 16CR57 8 bit General Purpose Register for 16C54,
16CR54, 16C56, 16CR56, 16C58 and 16CR58

TRIS Register
Tri-state Register O/p driver control register
Sets the Direction of the IO pins 1 puts the pin in Hi-Impedance Mode 0 puts the contents of the output data latch on the selected pins Write Only At reset TRIS are set and all I/Os in I/P mode

IO Ports
All Pins are individually Programmable Write to Latch
The data remain unchanged until rewritten

Read from Pin

Not latched, The data must be present until read by an instruction.

TIMER0
8-bit Timer Counter register
Readable and Writable

8-bit software programmable Prescalar

Set by OPTION Register

Internal Or External Clock Select

Rising or Falling Edge Select for External Clock

TIMER0
External Clock requirements
External Clock Synchronization Sampling the PreScalar output on Q2 and Q4 T0CKI High for at least 2 TOSC T0CKI Low for at least 2 TOSC

Prescalar Unit
8-bit Counter
Available to Timer0 or WDT

The divide Down Ratio is Selected by OPTION register

PreScalar Assignment
Changing Prescalar from WDT p Timer0
Clear WDT Load Desired Prescalar value for the Timer0

PreScalar Assignment
Changing Prescalar from Timer0 p WDT
Clear WDT Clear TMR0 Load Maximum Prescalar Value Clear WDT Load Desired Prescalar value for the WDT

STACK
9/10/11 bit two level stack h/w stack CALL ->
PUSH STACK1 -> STACK2; PC -> STACK1

RETLW ->
STACK1 -> PC; STACK2 -> STACK1

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