EED 4403 Design of Microprocessor-Based Systems

Hasrulnizam, Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901
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Connections Between CPU and Memory

Control signals

8088

Memory
Data Bus Address bus

What are the control signals from the microprocessor to memory? What are the control signal from memory to the microprocessor? Address and data signals should be buffered
The use of buffers on address bus increases driving capability Bi-directional buffers are used to control the data transferring directions on data bus D latches are used to de-multiplex signals on AD[7:0] (and A[19:16])
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Timing Diagram of A Memory Operation

Example: 8088 sends address 70C12 to memory in a memory read operation assume that data 30H is read
T1
Addr[15:0] D latch

T2

T3

T4

CLK ALE A[19:16] A[15:8] 7H 0CH 30H S3-S6

8088

A[15:8] Buffer AD[7:0] D latch D[7:0]

Memory

AD[7:0] 12H

DT/R DEN IO/M WR RD

Trans -ceiver

Addr[19:16] Addr[15:8] Addr[7:0] D[7:0]

7H 0CH 12H 30H

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Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips
Solution 1:

256KB
CS Addr[17:0] Addr[18] Addr[19] CS IO/M

256KB
CS

256KB
CS

256KB
CS

2-to-4 decoder

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Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips
Solution 2:

256KB
CS Addr[19:2] Addr[1] Addr[0] CS IO/M

256KB
CS

256KB
CS

256KB
CS

2-to-4 decoder

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Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips
Solution 3:

256KB
Addr[19:18] Addr[16:7] Addr[5:0] Addr[17] Addr[6] CS IO/M CS

256KB
CS

256KB
CS

256KB
CS

2-to-4 decoder

It is a bad design, but still works! Does it work if the last memory chip is removed?
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Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips
Solution 4:

256KB
CS Addr[17:0]

256KB
CS

512KB
CS

Addr[18] Addr[19] IO/M Addr[18] Addr[19] IO/M

Addr[18] Addr[19]

IO/M 5-7

Memory Address Decoding

Using partial memory addressing space
Addr[19:0]
FFFFF
Highest address

0011 0 111 1111 0011 0 000 0000

1111 1111 0000 0000

37FFF 32KB 30000 00000

These 5 address lines are not changed. They set the base address These 15 address lines select one of the 215 (32768) locations inside the RAMs Lowest address

Addr[14:0] Addr[19] Addr[18] Addr[17] Addr[16] Addr[15] IO/M

32KB
CS

Can we design a decoder such that the first address of the 32KB memory is 37124H?

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Memory Address Decoding

Exercise Problem:
A 64KB memory chip is used to build a memory system with the starting address of
7000H. A block of memory locations in the memory chip are damaged.

FFFFH 3317H 3210H 0000H 64KB

7FFFFH 73317H 73210H 70000H 733FFH Replace this block 73200H

Damaged block

1M addressing space

1M addressing space
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Memory Address Decoding

A[19] A[18] A[17] A[16] IO/M

A[15:0]

64KB CS

A[15] A[14] A[13] A[12] A[11] A[10] A[9]

A[8:0]

512B CS

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Memory Address Decoding

Exercise Problem:
A 2MB memory chip with a damaged block (from 0DCF12H to 103745H) is used to
build a 1MB memory system for an 8088-based computer 1FFFFFH 512K 18FFFFH 103745H 0FFFFFH 0DCF12H 000000H Damaged block A[19] A[19:0] A[20] A[19:0] CS
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1FFFFFH

Use these two blocks 07FFFFH 512K 000000H

Memory Address Decoding

Partial decoding
Example:
 build a 32KB memory system by using four 8KB memory chips  The starting address of the 32KB memory system is 30000H 0011 0 11 1 1111 1111 1111 0011 0 11 0 0000 0000 0000
Chip #4 Chip #3 Chip #2 Chip #1 high addr. of chip #4 Low addr. of chip #4 high addr. of chip #3 Low addr. of chip #3 high addr. of chip #2 Low addr. of chip #2 high addr. of chip #1 Low addr. of chip #1

36000H 34000H 32000H 30000H

0011 0 10 1 1111 1111 1111 0011 0 10 0 0000 0000 0000 0011 0 01 1 1111 1111 1111 0011 0 01 0 0000 0000 0000 0011 0 00 1 1111 1111 1111 0011 0 00 0 0000 0000 0000

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Memory Address Decoding

Implementation of partial decoding
8KB
CS

8KB
CS

8KB
CS

8KB
CS

Addr[12:0] Addr[13] Addr[14]

IO/M
2-to-4 decoder

With the above decoding scheme, what happens if the processor accesses location 02117H, 32117H, and 9A117H? If two 16KB memory chips are used to implement the 32KB memory system, what is the partial decoding circuit? What are the advantage and disadvantage of partial decoding circuits?
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Generating Wait States

Wait states are inserted into memory read or write cycles if slow memories are used in computer systems Ready signal is used to indicate if wait states are needed
data Address 8088 decoder Ready Delay circuit memory

D clk

clr Q

clr D Q

Ready

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SRAM v.s. DRAM

Static Random Access Memory (SRAM) Storage element Dynamic Random Access Memory (DRAM) made up of many cells and each cell is referred to as a bit. The value of 1 when active and 0 when inactive.

Advantages

1. 2. 1. 2.

Fast No refreshing operations Large silicon area expensive

1.

High density and less expensive

Disadvantages

1. 2.

Slow Require refreshing operations

Applications

High speed memory applications, Such as cache

Main memories in computer Systems Temporarily store information on computers

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SDRAM v.s. DDR RAM

SDR SDRAM or Synchronous Random Access Memory is the result of DRAM evolution. This type of memory synchronizes the input and output signals with the system board. Its speed ratings are in MHz. SDRAM was introduced in 1996 and is still used today. SDRAM transmits every clock count at a specific time. DDR SDRAM (or Double Data Rate Random Access Memory) does the same but it does so twice every clock count. This makes DDR RAM twice as fast as SDRAM. Over the years, RAM has become very fast and efficient.
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Accessing DRAMs
DRAM block diagram
Addr[7:0] CAS Column decoder Row decoder

RAS

Storage Array

RAS CAS Addr[7:0] Row addr. Column addr.

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Accessing DRAMs
Address bus selection circuit
Row Address MUX Column Address To DRAM

RAS address decoder D Q set D Q Q set D Q set CAS

CLK IO/M

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Accessing DRAMs
Refreshing operations
Because leakage current will destroy information stored on DRAM capacitors periodic refreshing operations are required for DRAM circuits During refreshing operation, DRAM circuit are not able to response processors request to perform read or write operations How to suspend memory operations? DRAM controllers are developed to take care DRAM refreshing operations

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