EE 201A (Starting 2005, called EE 201B) Modeling and Optimization for VLSI Layout

Instructor: Email: Lei He LHE@ee.ucla.edu

Chapter 7 Interconnect Delay

7.1 Elmore Delay 7.2 High-order model and moment matching 7.3 Stage delay calculation

Basic Circuit Analysis Techniques

Network structures & state Output response Input waveform & zero-states Natural response vN(t) (zero-input response) Forced response vF(t) (zero-state response)

For linear circuits: v(t ) ! v N (t )  v F (t ) Basic waveforms

Step input Pulse input Impulse Input

Use simple input waveforms to understand the impact of network design

Basic Input Waveforms

1/ T -T/2 T/2

1 0

unit step function

pulse function of width T

unit impulse function

u(t)=

0 1

tu0

1 PT (t ) ! T

T T H (t ) : PT (t ) u (t  2 )  u (t  2 ) H (t ) ! 0

when T p 0

By definition u (t ) ! or

for t { 0 singular for t ! 0 s.t. for any ^ "0

g

H ( x ) dx

^

H (t )dt ! 1

du (t ) (t) ! dt

Step Response vs. Impulse Response

Definitions:
(unit) step input u(t) (unit) impulse input H(t) (Input Waveform) (unit) step response g(t) (unit) impulse response h(t) (Output Waveform)
du (t ) dt p p h(t ) !
t

Relationship

H (t ) !
t

dg (t ) dt

u (t ) ! H ( x )dx
g

g (t ) ! h( x ) dx
0

Elmore delay

TD ! g ' (t )t dt ! h(t )t dt
0 0

Analysis of Simple RC Circuit

R i (t )  v (t ) ! vT (t ) d (Cv (t )) dv (t ) i (t ) ! !C dt dt dv (t ) RC  v (t ) ! vT (t ) dt
state variable Input waveform vT(t)

i(t) R C v(t)

first-order linear differential equation with constant coefficients

Analysis of Simple RC Circuit

zero-input response:

(natural response)

dv(t ) RC  v (t ) ! 0 dt 1 dv(t) 1 t ! v N (t) ! Ke RC v(t) dt RC

dv(t ) RC  v (t ) ! v0 u (t ) step-input response: dt  t RC v F (t ) ! v0u (t ) v (t ) ! Ke  v0u (t )

match initial state: output response for step-input:

v (0) ! 0

K  v0u (t ) ! 0
t

v0
RC

v0u(t) v0(1-eRC/T)u(t)

v (t ) ! v0 (1  e

)u (t )

Delays of Simple RC Circuit

v(t) = v0(1 - e-t/RC) under step input v0u(t) v(t)=0.9v0 t = 2.3RC v(t)=0.5v0 t = 0.7RC Commonly used metric TD = RC (Elmore delay to be defined later)

Lumped Capacitance Delay Model

R = driver resistance C = total interconnect capacitance + loading capacitance Sink Delay: td = RC
N3

Rd
N2

Cload

driver
N

50% delay under step input = 0.7RC Valid when driver resistance >> interconnect resistance All sinks have equal delay

Lumped RC Delay Model

t D ! R d C load ! R d  int  C g C ! R d  0 L  Cg C
Minimize delay minimize wire length

N3

Rd
N2

Cload

driver
N

Delay of Distributed RC Lines

Vout(t)
Laplace Transform

Vout(s)

VIN
VOUT

R C

VOUT

VIN

VOUT C

1 Vout ( s ) ! s cosh sRC e x  ex cosh( x ) ! 2 x2 x4 ! 1    ...... 2! 4!

1.0

DISTRIBUTED

0.5

LUMPED

1.0RC

2.0RC

time

Step response of distributed and lumped RC networks. A potential step is applied at VIN, and the resulting VOUT is plotted. The time delays between commonly used reference points in the output potential is also tabulated.

Delay of Distributed RC Lines (contd)

Output potential range Time elapsed (Distributed RC Network) 1.0 RC 0.9 RC 0.5 RC 0.4 RC 0.1 RC Time elapsed (Lumped RC Network) 2.3 RC 2.2 RC 1.0 RC 0.7 RC 0.1 RC

0 to 90% 10% to 90% (rise time) 0 to 63% 0 to 50% (delay) 0 to 10%

Distributed Interconnect Models

Distributed RC circuit model
L,T or 4 circuits

Distributed RCL circuit model Tree of transmission lines

Distributed RC Circuit Models

Distributed RLC Circuit Model (without mutual inductance)

Z0

Z0

Delays of Complex Circuits under Unit Step Input

Circuits with monotonic response
1 T50% 0.5
TR v(t)

Easy to define delay & rise/fall time Commonly used definitions

Delay T50% = time to reach half-value, v(T50%) = 0.5Vdd Rise/fall time TR = 1/v(T50%) where v(t): rate of change of v(t) w.r.t. t Or rise time = time from 10% to 90% of final value

Problem: lack of general analytical formula for T50% & TR!

Delays of Complex Circuits under Unit Step Input (contd)

Circuits with non-monotonic response

Much more difficult to define delay & rise/fall time

Elmore Delay for Monotonic Responses

v(t)

Assumptions:
Unit step input Monotone output response

1 0.5 T50% v(t) t

Basic idea: use of mean of v(t) to approximate median of v(t)

v(t ) : output response (monotone) v' (t ) : rate of change of v(t )
median of v(t) (T50%)
TD ! tv ' (t ) dt
0 g

mean of v'(t)

Elmore Delay for Monotonic Responses

T50%: median of v(t), since

T50%

v ' (t )dt !

g

T50%

v ' (t )dt

! half of final value of v (t ) (by def.)

Elmore delay TD = mean of v(t)

TD !

v' (t )tdt

Why Elmore Delay?

Elmore delay is easier to compute analytically in most cases Elmores insight [Elmore, J. App. Phy 1948] Verified later on by many other researchers, e.g. Elmore delay for RC trees [Penfield-Rubinstein, DAC81] Elmore delay for RC networks with ramp input [Chan, TCAS86] ..... For RC trees: [Krauter-Tatuianu-Willis-Pileggi, DAC95] T50% e TD Note: Elmore delay is not 50% value delay in general!

Elmore Delay for RC Trees

h(t) = impulse response

Definition h(t) = impulse response TD = mean of h(t)

g

H(t) = step response

h(t) t dt
0

Interpretation g H(t) = output response (step process) median TD ! tv ' (t ) dt 0 of v(t) mean of v'(t) h(t) = rate of change of H(t) (T50%) T50%= median of h(t) Elmore delay approximates the median of h(t) by the mean of h(t)

Elmore Delay of a RC Tree

[Rubinstein-Penfield-Horowitz, T-CAD83]
Lemma: when a step input is applied to a RC tree vi (t ) is monotonic in t for every node i in tree Proof: v 'i (t ) u 0 at every node i (v ' i (t ) ! hi (t ))
impulse response hi (t ) u 0 at every node i
Apply impulse func. at t=0:

Let hmin (t ) be the min. voltage of any node at t hmin (0) u 0 Assume that hmin (t0 ) 0 Then, t1 t0 s.t. h'min (t1 ) 0

imin

Let node imin achieve hmin (t1 ) at t1 Then, the current from any node i to imin is u 0 at t1 Since hi (t1 ) u hmin (t1 ) & i connects imin via resistors
i

current ipimin

Since all currents i p imin charge the capacitor at imin h'min (t1 ) u 0 contradiction!

Elmore Delay in a RC Tree (contd)

Pi : path from input to node i ; si :subtree rooted at i R jk : resistance of common path Pj Pk from input to j & k

Si i

path resistance Rii input Rjk

Theorem : Elmore delay to node i

TDi ! Rki Ck
k

Proof :

dvi (t ) dt 1  vi (t ) ! The voltage drop on Pi ! Rk (current to all cap' s in S i ) The current to cap. of node i ! Ci
kPi

! (current to cap k ) (common path res. between Pi and Pk )

k

! Ck
k g 0

dvk (t ) dv (t ) Rki ! Rki Ck k dt dt k

g 0

TDi ! v 'i (t )t dt ! vi (t ) t |g  vi (t )dt 0 ! lim[vi (T ) T  vi (t )dt ] ! lim (vi (T )  1) T  (1  vi (t ))dt

T pg 0 T pg 0 T g

Elmore Delay in a RC Tree (contd)

lim We shall show later on that T pg (1  vi (T )) T ! 0 i.e. 1-vi(T) goes to 0 at a much faster rate than 1/T when Tpg

Let

f i (t ) ! [1  vi ( x)]dx
0

dv ( x) f i (t ) ! Rki Ck k dx 0 dx k
t

vi(t) 1

area

f i (t ) ! [1  vi ( x)]dx
0

! Rki Ck v k (t )
k

! Rki Ck  Rki Ck [1  vk (t )]
k k

f i (g) ! Rki Ck
k

(1) 0
g

@ TDi ! lim (1  vi (T ))T  [1  vi (t )]dt

T pg 0

! f i (g) ! Rki Ck
k

Some Definitions For Signal Bound Computation

Let T p ! Rkk Ck
k 2 TRi ! ( Rki Ck ) Rii k

Recall TDi ! Rki Ck

k

Then,

TRi e TDi e T p

(since Rkk u Rki & Rii u Rki )

Signal Bounds in RC Trees

Theorem
Lower bounds 0 TDi vi (t ) u 1  t  TRi 1 TDi Tp
(T p TRi )

tu0 t u 0 (non - trivial when t u TDi  TRi )

Tp

t

Tp

t u T p  TRi

Upper bounds TD  t 1 i Tp v i (t ) e 1 TRi Tp

(TDi TRi ) t

t u0

TRi

TRi

t u TDi  TRi

Delay Bounds in RC Trees

Lower bounds : t u TD i  Tp ?  vi (t )A 1 t u TDi  TRi  TRi ln TRi Tp ?  vi (t )A 1 when vi (t ) u 1  TRi Tp

Upper bounds : TDi te  TRi 1  vi (t ) TDi t e Tp  TRi  Tp ln Tp ?  vi (t )A 1 when vi (t ) u 1  TDi Tp

Computation of Elmore Delay & Delay Bounds in RC Trees

Let C(Tk) be total capacitance of subtree rooted at k Elmore delay
TDi ! upper bound : Tp ! Rk C (Tk )
k

R
k pi

C (Tk )

lower bound :
2 TRi ! Rki k

Ck Rii

* all three formula can be computed in linear time recursively in a bottom - up fashion

Comments on Elmore Delay Model

Advantages
Simple closed-form expression
Useful for interconnect optimization

Upper bound of 50% delay [Gupta et al., DAC95, TCAD97]

Actual delay asymptotically approaches Elmore delay as input signal rise time increases

High fidelity [Boese et al., ICCD93],[Cong-He, TODAES96]

Good solutions under Elmore delay are good solutions under actual (SPICE) delay

Comments on Elmore Delay Model

Disadvantages
Low accuracy, especially poor for slope computation Inherently cannot handle inductance effect
Elmore delay is first moment of impulse response Need higher order moments

Chapter 7.2 Higher-order Delay Model

Time Moments of Impulse Response h(t)

Definition of moments

h(t ) L H ( s ) p H ( s ) ! h(t )e  st dt !
0 g g g 0

g 1 i h(t ) ( st ) dt i !0 i!

g 1 i ! ( s ) h(t ) t i dt 0 i ! 0 i! g 1 i i-th moment mi ! (1) h(t ) t i dt 0 i!

Note that m1 = Elmore delay when h(t) is monotone voltage response of impulse input

Pade Approximation
H(s) can be modeled by Pade approximation of type (p/q):

H p ,q ( s ) !
where q < p << N

bp s p  .  b1s  b0 aq s  .  a1s  1
q

Or modeled by q-th Pade approximation (q << N):

kj H q ( s ) | H q1,q ( s ) ! j !1 s  p j
Formulate 2q constraints by matching 2q moments to compute kis & pis

General Moment Matching Technique Basic idea: match the moments m-(2q-r), , m-1, m0, m1, , mr-1

H (s) !

kq k1 k2  .  s  p1 s  p2 s  pq

! m0  m1s  .  mr 1s r 1  3( s r )

When r = 2q-1:
(i) initial condition matches, i.e.

h(0 ) ! h(0 ), or lim sH ( s ) ! lim sH ( s )

s pg s pg

or ( m1 ! m1 )
(ii)

mk ! mk for k ! 0,1, . ,2q  2

moments of H ( s )

Compute Residues & Poles

3 @
EQ1

ki k p k ! i i ! i s  pi 1  s pi pi

(
j !0

s j ) pi ( ! lim sH ( s ))
s pg

k1  k 2  .  k q ! h(0) ! m1 kq k1 k 2 (   .  ) ! m0 p1 p2 pq kq k1 k 2  ( 2  2  .  2 ) ! m1 p1 p2 pq /

initial condition

match first 2q-1 moments

kq k1 k2  ( 2 q 1  2 q 1  .  2 q 1 ) ! m2 q  2 p1 p2 pq

Basic Steps for Moment Matching

Step 1: Compute 2q moments m-1, m0, m1, , m(2q-2) of H(s) Step 2: Solve 2q non-linear equations of EQ1 to get

p1 , p2 , . , pq : poles k1 , k 2 , . , k q : residues
Step 3: Get approximate waveform

(t ) ! k e p1t  k e p2t  .  k e pq t h q 1 2
Step 4: Increase q and repeat 1-4, if necessary, for better accuracy

Components of Moment Matching Model

Moment computation
Iterative DC analysis on transformed equivalent DC circuit Recursive computation based on tree traversal Incremental moment computation

Moment matching methods

Asymptotic Waveform Evaluation (AWE) [Pillage-Rohrer, TCAD90] 2-pole method [Horowitz, 1984] [Gao-Zhou, ISCAS93]...

Moment calculation will be provided as an OPTIONAL reading

Chapter 7 Interconnect Delay

7.1 Elmore Delay 7.2 High-order model and moment matching 7.3 Stage delay calculation

Stage Delay
Source A B Interconnect C Load

TAC ! TAB ( I , L)  TBC ( L) TAB (0, L) : Gate delay without interconnect TAB ( I , L) : Gate delay with interconnect TBC ( L) : Propagation delay  Transition delay TInterconnect ! TAB ( I , L)  TAB (0, L)  TBC ( L)

Modeling of Capacitive Load

First-order approximation: the driver sees the total capacitance of wires and sinks Problem: Ignore shielding effect of resistance pessimistic approximation as driving point admittance Transform interconnect circuit into a T-model [OBrian-Savarino, ICCAD89]
Problem: cannot be easily used with most device models

Compute effective capacitance from T-model [Qian-Pullela-Pileggi, TCAD94]

4-Model [OBrian-Savarino, ICCAD89]

Moment matching again! Consider the first three moments of driving point admittance (moments of response current caused by an applied unit impulse) Current in the downstream of node k
I k (s) !

C sV (s)
j j jTk

Yk ( s ) ! I k ( s ) / Vin ( s) Yk ( s ) ! !

C sH
j jTk jTk

( s)
g (1) j ( 2) 2 j

C j s (1  m s  m s  . ) ! C j m (ji ) s i 1
i !1 jTk

Driving-Point Admittance Approximations

Driving-point admittance = Sum of voltage momentweighted subtree capacitance
( y ki ) !

C j m (ji 1)
jTk g

( Yk ( s ) ! yki ) s i i !1

Approximation of the driving point admittance at the driver Y (s)

General RC Tree: lumped RC elements, distributed RC lines

Driving-Point Admittance Approximations

First order approximation: y(1) = sum of subtree capacitance (1)
Y ( s)

C ! y (1)
Second order approximation: yk(2) = sum of subtree capacitance weighted by Elmore delay
Y ( 2) ( s)

R ! y

( 2)

/( y )

(1) 2

C ! y (1)

Third Order Approximation: 4 Model

Y ( 3) ( s )

C2

C1 (y ) C1 ! ( 3) y
(1) ( 2) 2

y (1) ! C1  C2

y ( 2) !  RC12
y (3) ! R 2C13

C2 ! y  C1 y ( 2) R! 2 C1

Current Moment Computation

Similar to the voltage moment computation Iterative tree traversal:

O(n) run-time, O(n) storage

Bottom-up tree traversal:

O(n) run-time Can achieve O(k) storage if we impose order of traversal, k = max degree of a node OBrian and Savarino used bottom-up tree traversal

Bottom-Up Moment Computation

Maintain transfer function Hv~w(s) for sink w in subtree Tv, and moment-weighted capacitance of subtree:

m for j ! 0 - p, C for j ! 0 - p  1
j w j Tv

p u

As we merge subtrees, compute new transfer function Hu~v(s) and weighted capacitance recursively:
q CTvj 1 ! mvj 1Cv  mvj 1 q CTv , q !0 j 1

p 1 Tu

Rv , Lv , Cv mvp
CTpv 1

mvj ! ( Rv CTvj 1  LvCTvj  2 ) for j ! 1- p

New transfer function for node w

mvp
v

CTp 1 v

H u ~ w ( s) ! H u ~ v ( s ) v H v ~ w ( s )
q mwj ! mvj  q mw for j ! 0 - p q !0 j

New moment-weighted capacitance of Tu:

CTuj !

vchild ( u )

CTvj for j ! 0 - p  1

p mw

mwp

Current Moment Computation Rule #1

YU (s )
YD (s)

( (1 yU1) ! y D )  C ( ( yU2) ! y D2) ( ( yU3) ! y D3)

Current Moment Computation Rule #2

YU (s )

YD (s)

(1) U

!y

(1) D

( ( (1 yU2) ! y D2)  R ( y D ) ) 2 ( ( (1 ( (1 yU3) ! y D3)  2 R ( y D ) )( y D2) )  R 2 ( y D ) ) 3

Current Moment Computation Rule #3

YU (s )

YD (s)

C
( (1 yU1) ! y D )  C

( 2) U

!y

(2) D

1 2 (1) 2 (1)  R ( y D )  C ( y D )  C 3

( ( (1 ( ( yU3) ! y D3)  R 2( y D ) )( y D2) )  C ( y D2) ) 

2 2 (1) 2 3 (1) 3 4 (1) 2 R ( y D )  C ( y D )  C ( y D )  C 3 3 15

2

Current Moment Computation Rule #4 (Merging of Sub-trees)

YD1 ( s )
( (1 yU1) ! y Di) i !1 ( (2 yU2) ! y Di) i !1 ( (3 yU3) ! y Di) i !1 B B B

YU (s )

B Branches

YDB (s )

Example: Uniform Distributed RC Segment

Purely capacitive

TAB/TAB(0)
Wide metal (distributive) Wide metal (T) Wide metal (lumped RC) Narrow metal (T) Narrow metal (distributive)

Narrow metal (lumped RC)

Cload/Cmax

Why Effective Capacitance Model?

The T-model is incompatible with existing empirical device models
Mapping of 4D empirical data is not practical from a storage or run-time point of view

Convert from a T-model to an effective capacitance model for compatibility Equate the average current in the T-load and the Ceff load

X in

C2

C1

X in

Ceff

Equating Average Currents

IT
R C1

IC

X in

C2

X in

Ceff

1 tD

tD

1 I T (t ) dt ! tD

tD

I C (t )dt

I T ( s ) ! YT ( s )Vout ( s ) I C ( s ) ! sCeff Vout ( s )

tD = time taken to reach 50% point, not 50% point of input to 50% point of output

Waveform Approximation for Vout(t)

Quadratic from initial voltage (Vi = VDD for falling waveform) to 20% point, linear to the 50% point

i  ct 2 V Vout (t ) ! a  b(t  t x )
2 a ! Vi  ct x

0 e t e tx tx e t e tD

Voltage waveform and first derivative are continuous at tx

b ! 2ct x

Average Currents in Capacitors

tD 1 tx I C (t ) ! Ceff (2ct ) dt  Ceff ( 2ct x ) dt tx t D 0

 2Ceff c t x tD

[t D 

tx ] 2

I C2 (t ) !

t  2C2 c t x [t D  x ] tD 2

Average current of C1 is not quite as simple:

Current due to quadratic current in C2 Current due to linear current in C2

Average Currents in C1
Average current for (0,tx) in C2
t x 2  2C1 c t x RC1 2  RC1t x  ( RC1 ) 1  e I C1 (t ) ! tx 2

Average current for (tx,tD) in C2

t x  ( t D t x )  C1 c RC1 RC1 2 2 RC1t x  2( RC1 ) 1  e 1 e I C1 (t ) ! tD  t x

RC1 1   2ct xC1 tD  tx

( t D t x ) RC1 1  e

Average current for (0,tD) in C2

tD D 2  ( tRCt x )  2C1 c t x RC1 2 1  t x t D  t x  RC1  ( RC1 ) e I C1 (t ) ! e tD 2

Computation of Effective Capacitance

Equating average currents Ceff
tD 2  ( t D t x ) RC1 ( RC1 ) RC1 RC1 e ! C2  C1 1   e tx tx t D  2 t x (t D  2 )

Problem: tD and tx are not known a priori Solution: iterative computation

Set the load capacitance equal to total capacitance Use table-lookup or K-factor equations to obtain tD and tx

t D ! t d  X in / 2 tx ! tD  X / 2
Equate average currents and calculate effective capacitance Set load capacitance equal to effective capacitance and iterate

Stage Delay Computation

Calculate output waveform at gate
Using Ceff model to model interconnect

Use the output waveform at gate as the input waveform for interconnect tree load Apply interconnect reduced-order modeling technique to obtain output waveform at receiver pins