CMOS Circuit Design for Minimum Dynamic Power and Highest Speed

Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn University Michael L. Bushnell, Dept. of ECE, Rutgers University
Research Funded by: A National Science Foundation Grant

Talk Outline
Motivation  Objective  Prior Work  New Approach  Results  Conclusion and Future Work


Jan 9, 2004

Int'l Conf. on VLSI Design, 2004

Motivation


Power consumption due to glitches can exceed 3040% of total power consumption. Existing linear programming techniques eliminate glitches, but may insert delay buffers when overall circuit delay is constrained. Delay buffers consume power themselves and thus reduce power saving also chip area increases. Example: c1355, a 619-gate circuit needed 224 buffers -- 36 % increase in gates for 42% power saving and no IO delay increase.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 3

Problem Statement


Find a linear program (LP) to determine gate delays in a CMOS circuit such that:

All glitches are eliminated No delay buffers are inserted in the circuit Circuit operates at the highest possible speed
permitted by the device technology.
Note: The objective is to minimize switching power. Hence, no attempt is made to reduce short-circuit and leakage power, which is an order of magnitude lower for present CMOS technologies; those components of power may be addressed in the future research.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 4

CMOS Power Dissipation

  

Short circuit power Leakage power (IDDQ) Dynamic power

Essential transitions Glitches Each transition dissipates CV2/2

Short circuit and leakage power components are at least an order of magnitude lower than the dynamic power in present day technologies.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 5

What Are Glitches?

Delay =1 2

  

Glitches occur due to differential (unbalanced) path delays. Glitches are transients that are unnecessary for the correct functioning of the circuit. Glitches waste power in CMOS circuits.
Int'l Conf. on VLSI Design, 2004 6

Jan 9, 2004

Glitch Suppression


Differential Path Delay

Path P1

Path P2

Differential Delay = |delay (P1) delay (P2)|; it is the width of the maximum potential glitch at the gate output.  For complete glitch suppression: for each gate, inertial delay > differential delay  To satisfy this condition, previous low-power design methods insert delay buffers in the circuit.  Power will be further reduced if glitch suppression could be achieved without buffers.

Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 7

Example: Why Use Buffers?

1 1

Critical path delay = 3

Delay unit is the smallest delay possible for a gate in a given technology.  Critical Path is the longest delay path in the circuit and determines the speed of the circuit.

Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 8

Example (cont.)
0 1 0 1

time
1

For glitch free operation of first gate:

 

Differential delay at inputs e inertial delay OK

Int'l Conf. on VLSI Design, 2004 9

Jan 9, 2004

Example (cont.)
1 1 1 0 1

For glitch free operation of second gate:

 

Differential delay at inputs e inertial delay OK

Int'l Conf. on VLSI Design, 2004 10

Jan 9, 2004

Example (cont.)
1 1 2 1 0

For glitch free operation of third gate:

 

Differential delay at inputs e inertial delay Not true for gate 3

Int'l Conf. on VLSI Design, 2004 11

Jan 9, 2004

Example (cont.)
1 1 2 1 1 1

For glitch free operation with no IO delay increase: Must add a delay buffer.  Buffer is necessary for conventional gate design only gate output delay is controllable.

Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 12

Controllable Input Delay Gates

1 1 2 1 2 0

Assume gate input delays to be controllable  Glitches can be suppressed without buffers


Jan 9, 2004

Int'l Conf. on VLSI Design, 2004

13

Delay Model for a New Gate

1 2
    

d3,1 + d3 d3,2 + d3

Separate the output (inertial) and input delay components. d3 - output delay of the gate. d3,1 - input delay of the gate along path from 1 to 3. Gate design is feasible and is under development... Technology constraint: input delay difference has an upper bound, which we define as Gate Input Differential Delay Upper Bound ( ub ).
Int'l Conf. on VLSI Design, 2004 14

Jan 9, 2004

Gate Input Differential Delay Upper Bound (ub) (u

It is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a given CMOS technology.  Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and layout levels.  The bound ub is the limit of flexibility allowed by the technology to the designer at the transistor and layout levels.  The following feasibility condition must be imposed while determining delays for glitch suppression:


0 e di, j e ub
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 15

A New Linear Program



Contains following components

Variables
  

Gate inertial delay variables (di) Input delay variables (di,j) Timing window variables Gate delay constraints Gate input delay upper bound constraints Differential delay constraints Maximum delay constraints

Constraints
   

Objective function


Let us consider a simple example combinational circuit.

Int'l Conf. on VLSI Design, 2004 16

Jan 9, 2004

New LP Example
1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5

2
d6,2 + d6

3 4
  

d6,3 + d6

Gate inertial delay variables d5 ..d7 Gate input delay variables di, j for every path through gate i from input j Corresponding window variables t5 ..t7 and T5 ..T7.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 17

New LP Example (cont.)

1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5 d6,2 + d6

3 4
 

d6,3 + d6

Inertial delay constraint for gate 5: d5 Input delay constraints for gate 5:

u1

0e 0e

d5,1 e ub d5,2 e ub
Int'l Conf. on VLSI Design, 2004 18

Jan 9, 2004

New LP Example (cont.)

1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5

2
d6,2 + d6

3 4


d6,3 + d6

Differential delay constraints for gate 5:

T5 > T5,1 + d5; t5 < t5,1 + d5; T5 > T5,2 + d5; t5 < t5,2 + d5;
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004

d5 > T5 t5;
19

New LP Example (cont.)

1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5

2
d6,2 + d6

3 4


d6,3 + d6

Differential delay constraints for gate 5:

T5,1 > T5 + d5,1; T5,2 > T5 + d5,2; t5,1 < t5 + d5,1; t5,2 < t5 + d5,2;
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 20

New LP Example (cont.)

1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5

2
d6,2 + d6

3 4


d6,3 + d6

IO delay constraint for each PO in the circuit:

T7 e maxdelay;
maxdelay is the parameter which gives the delay of the critical path. This determines the speed of operation of the circuit.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 21

New LP Example (cont.)

1
d5,1 + d5

5
d7,5 + d7 d7,6 + d7 d7,4 + d7

d5,2 + d5

2
d6,2 + d6

3 4
 

d6,3 + d6

Objective Function:

minimize maxdelay;

This gives the fastest and lowest dynamic power consuming circuit, given the feasibility condition for the technology.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 22

Solution Curves
Power Previous solutions with buffers
Power consumed by buffers

New solutions

Minimum Dynamic power

ub=

ub=15 ub=10 ub=5

ub=0

Fastest Possible Design

Jan 9, 2004 Int'l Conf. on VLSI Design, 2004

Maxdelay
23

Results: Results: Procedure Outline

Combinational circuit netlist C++ Program Constraint-set AMPL Optimized delays Power Estimator Results
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 24

Results on Feasibility Upper Bound (ub)

   

Maxdelay is normalized to the fastest possible circuit design. Each curve is a different benchmark circuit. As we increase ub, the circuit becomes faster. Flexibility required for fastest operation of circuit is proportional to the size of the circuit.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 25

Results: Low-Power Design LowCircuit Unoptimized Optimized power power No. of vectors maxdelay Norm. delay

ub 5 10 15 0 5 10 15 10 15
26

c432

1.0 1.0 1.0

0.52 0.49 0.48 0.70 0.75 0.48 0.47 0.47 0.46

56 56 56 54 54 78 78 87 87

71 27 17 34 15 45 30 71 46

4.17 1.58 1.00 2.26 1.00 1.50 1.00 2.95 1.91

c499 c880 c1355

1.0 1.0 1.0 1.0 1.0 1.0

Jan 9, 2004

Int'l Conf. on VLSI Design, 2004

Comparison with Conventional Gate al., Des. Design (ub=0) (Raja et al., VLSI Des. `03) (u
Conventional gates Circuit c432 c499 c880 c1355 Power 0.72 0.62 0.91 0.70 0.68 0.68 0.58 0.57
Jan 9, 2004

Variable input delay gates Power 0.48 0.49 0.75 0.70 0.47 0.48 0.46 0.47 maxdelay 1.0 1.58 1.00 2.26 1.00 1.50 1.00 2.08

maxdelay 1.0 2.0 1.4 2.2 1.0 2.0 1.0 2.0

Buffers 95 66 48 0 62 34 224 192

ub
15 10 15 10 15 10 15 10
27

Int'l Conf. on VLSI Design, 2004

Conclusion


Main idea: Minimum dynamic power circuits can be designed if gates with variable input delays are used.

The new design suppresses all glitches without any delay buffers.

Speed of the new design depends on the gate input delay variability allowed by the technology.

  

A linear program solution demonstrates the idea. Results show average power savings up to 52%. Future work: Variable input delay gate design.
Int'l Conf. on VLSI Design, 2004 28

Jan 9, 2004

Thank you

Jan 9, 2004

Int'l Conf. on VLSI Design, 2004

29