Delay-based Spread Spectrum Clock Generator

Subramaniam Venkatraman Matthew Leslie University of California, Berkeley EE 241 Final Presentation May 9th 2005

Motivation

In digital systems, the most amount of electromagnetic interference (EMI) is caused by the high-speed digital clock Strict FCC regulations on maximal permitted EMI Traditional solutions: shielding the chip, filtering the clock signal Solution: Spread the spectrum of the clock over a small frequency range within the timing margin (usually +/- 1%) so peak emission is attenuated Often accomplished by modulating the frequency of the VCO in a PLL
[Keith B. Hardin, Spread Spectrum Clock Generation for the Reduction of Radiated Emissions]

Delay Cell Array Based Approach

SSCG usually implemented with 50KHz modulation waveform to prevent interference with FM systems PLL is required to have a large loop bandwidth hence making it more susceptible to noise Leads to large jitter in clock which is unacceptable Instead can be implemented with a variable delay elements which introduce appropriate delays and shift the effective frequency Leads to smaller random jitter, simpler implementation and reduction in area The idea has been reported but uses 200 delay stages and shows unnatural clock waveform with maximum energy in the 4th harmonic 0.35 CMOS technology used to compare with reported results from Jonghoon Kim et al.

Digital Delay Array

Each delay cell comprised of delay element and a positive latch:
Delay Cell #1 Q D EN Delay Cell #2 Q D EN Delay Cell #N

D EN

Result: Edge-to-edge jitter varied in deterministic fashion.

Edge-to-Edge Jitter (normalized to maximum) 1.2 1 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 kth Transition Edge

Digital Delay Array Element

Characteristics: Delay varies linearly with Lx. All elements have identical off delay. Keeps tpLH and tpHL the same. Identical fanout independent of delay

W/Lx

tpHL and tpLH

Comparison of Clock Attenuation Reported results show: Our results show:

Large power in even clock harmonics Percentage spread not constant with frequency

Dominant power in odd harmonics Percentage spread constant with frequency

[Jonghoon Kim; 2004 IEEE international symposium on electromagnetic compatibility]

Improved Design

For a 1GHz system with 50KHz modulating waveform, number of stages in earlier design would be 20,000 Removes the direct dependency of number of stages on the ratio between clock frequency and modulation frequency which is major limiting factor in previous design Triangular modulation waveform applied to delay elements would lead to clock pulses with equal period and therefore constant frequency Create modulation waveform needed by integrating the triangular wave Use this modified waveform to control the current through a current-starved differential delay element Non linearity in improved design can be corrected by changing input waveform
50
1400

g( t )

f( t )
h( t )

1 0 t 200

50 0 t 200

100 0 t 200

Improved Design

Jitter is dictated by two characteristics of the delay element: the power supply rejection ratio (PSRR), represented by the numerator the maximum slope at the switching-point of each delay element, represented by the denominator. Differential stage provides high PSRR Latch based design provides reduced rise and fall time

Comparison with MATLAB Results

Triangular modulation causes non ideal frequency spread but the error caused is 1.7dB and simplifies implementation Our implementation shows greater spread than designed for due to non-linearity of analog delay element

Comparison of Results
Reported Power consumption Area Jitter with clean vdd Jitter with 50mV p-p supply noise Attenuation 120mW 3400m*90m 9dB on 4th harmonic Our simulation of Our design reported work 132mW 3290*90(m)2 7.09ps 30.10ps 7dB on fundamental 8.6mW 13*90(m)2 9.45ps 29.76ps 8dB on fundamental

Conclusions & Future Work

Delay cell based SSCG implemented shows low power and simple circuit implementation 8dB of clock attenuation on fundamental Approach requires constant number of delay stages with increasing clock frequency unlike previous reported result Modulation frequency not hard-coded in the circuit The linearity of the delay stage needs to be improved either using circuit techniques or by compensating initial input signal Jitter can be reduced by trading off with number of stages An actual implementation would be needed to test for actual jitter caused and clock attenuation achieved