Lecture 6 Lecture 6 Logic Simulation Logic Simulation

s s s s

What is simulation? Design verification Circuit modeling True-value simulation algorithms

s s

Compiled-code simulation Event-driven simulation

Summary

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

Simulation Defined Simulation Defined

s s

Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification:
s s s

Validate assumptions Verify logic Verify performance (timing) Logic or switch level Timing Circuit Fault (Lecture 7)
VLSI Test: Lecture 6 2

Types of simulation:
s s s s

Copyright 2001, Agrawal & Bushnell

Simulation for Simulation for Verification Verification

Specification Synthesis Response analysis Design changes Design (netlist)

Computed responses

True-value simulation

Input stimuli

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

Modules, blocks or components described by

s s s

Modeling for Modeling for Simulation Simulation

Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors ideal signal carriers, or ideal electrical conductors

Interconnects represent
s s

Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.
VLSI Test: Lecture 6 4

Copyright 2001, Agrawal & Bushnell

Example: A FullExample: A FullAdder HA; Adder c

e d f

HA
Half-adder

inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e);

A B C

HA1

D E

HA2

Carry Sum

Full-adder

FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry);
5

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

pMOS FETs a Ca b Cb

Logic Model of MOS Logic Model of MOS Circuit Circuit

VDD a c Cc nMOS FETs b Da Db Dc c

Da and Db are interconnect or propagation delays Dc is inertial delay of gate

Ca , Cb and Cc are parasitic capacitances

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 6

Options for Inertial Options for Inertial Delay Delay

Inputs a b c (CMOS) Logic simulation c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) 0
Copyright 2001, Agrawal & Bushnell

(simulation of a NAND gate) (simulation of a NAND gate)

Transient region

X Unknown (X) 5
VLSI Test: Lecture 6

rise=5, fall=5 min =2, max =5 Time units

7

Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits.
Z (hold previous value) 0 0
VLSI Test: Lecture 6 8

Signal States Signal States

Copyright 2001, Agrawal & Bushnell

Modeling Levels Modeling Levels

Modeling level Function, behavior, RTL Logic Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z Timing Clock boundary Zero-delay unit-delay, multipledelay Zero-delay Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification
9

Switch

0, 1 and X Analog voltage Analog voltage, current

Timing

Fine-grain timing Continuous time

Circuit

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

Compiled-code simulation
s s

True-Value Simulation True-Value Simulation Algorithms Algorithms

s

Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for lowactivity circuits High-level (e.g., C language) models can be used Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation
VLSI Test: Lecture 6 10

Event-driven simulation
s

s s s

Copyright 2001, Agrawal & Bushnell

Compiled-Code Compiled-Code Algorithm Algorithm

s s s

Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flip-flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations)
s

Execute compiled code

Report or save computed variables

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

11

Event-Driven Event-Driven Algorithm Algorithm

(Example) (Example)
g=1 d=0 b=1 4 2 f=0 Time stack
Scheduled events c=0 Activity list d, e

a=1 c=1

0 2

e=1

t=0 1 2 3 4 5 6

d = 1, e = 0

f, g

g=0

g
0 4 8

f=1

Time, t

7 8 g=1
12

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

Time Wheel (Circular Time Wheel (Circular Stack) Stack)

Current time pointer max t=0 1 2 3 4 5 6 7 Event link-list

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

13

Efficiency of EventEfficiency of EventDriven Simulator Driven Simulator

s s

Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change
Steady 0 0 1 event

Steady 0 (no event)

Large logic block without activity

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

14

Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator.

Summary Summary

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 6

15