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Today's microprocessors sport a general-purpose design which has its own advantages and disadvantages.
Advantage: One chip can run a range of programs.
That's why you don't need separate computers for different jobs, such as crunching spreadsheets or editing digital photos Disadvantage: For any one application, much of the chip's circuitry isn't needed, and the presence of those "wasted" circuits slows things down.
Chameleon computing
Software-programmed processors
Advantages: very high performance and efficient Disadvantages: not flexible (cant be altered after fabrication) expensive
Advantages: fills the gap between hardware and software much higher performance than software higher level of flexibility than ASICs
Advantages: software is very flexible to change Disadvantages: performance can suffer if clock is not fast fixed instruction set by hardware
integrated circuit (IC) customized for a particular use For example, a chip designed solely to run a cell phone is an ASIC. Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.
integrated circuit designed to be configured by the customer or designer after manufacturing. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together.
demanded by the particular software they are interfacing with at any given time.
Reconfigurable processor usually contains several parallel processing
design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.
particular software.
It takes just 20 microseconds to reconfigure the entire
processing array.
Reconfigurable
processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology). those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves.
Among
implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas.
configuration inputs and another as data or control inputs and outputs. A new chip must inside determine the set of the function blocks (FB), which are used to construct the circuit, rules of their interconnections and ways of the input/output connections. The most important parts are the logic circuits, which configure function blocks according to data in the configuration memory. The various possible connections between functional blocks are encoded to bits known as Configuration bits. Resulting configuration stream is downloaded into configuration memory through configuration inputs. Thus, a new Reconfigurable machine is established.
Configuration Subsystem
Chip. It consists of
84,32-bit Data path Units 24, 1624-bit Multipliers Operating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates
runtime Tiles contain : Datapath Units Local Store Memories 16x24 multipliers Control Logic Unit
eCONFIGURABLE TECHNOLOGY:
used
for
technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. As mentioned earlier, each Slice can be configured independently. Loading the Background Plane from external memory requires just 3 sec per Slice; this operation does not interfere with active processing on the Fabric. Swapping the Background Plane into the Active Plane requires just one clock cycle. with eConfigurable Technology;
are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms. The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing, debugging and verifying RCP designs. C~Side uses a combined C language and Verilog flow to map algorithms into the chips reconfigurable processing fabric (RPF).
System and the Fabric. eBIOS provides resource allocation, configuration management and DMA services. The eBIOS calls are automatically generated at compile time, but can be edited for precise control of any function.
highly integrated, high-performance semiconductor technologies, such as application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). However, system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility.
Enter the reconfigurable processor, an entirely new category of
semiconductor solution that serves as a system-level platform for a broad range of applications.
Early and fast design Reducing development cost Can more quickly adapt to new requirements and standards Increasing bandwidth Reducing power Reducing manufacturing cost.
Inertia Engineers slow to change Inertia is the worst problem facing reconfigurable
computing
RCP designs requires comprehensive set of tools 'Learning curve' for designers unfamiliar with reconfigurable
logic
base stations and their unpredictable combination of voice and data-traffic. Base-station infrastructure will have to be adaptive enough to accommodate those requirements. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections
Wireless Local Loop (WLL) Reconfigurable technology is widely applied
in Wireless Local Loops also because of their high processing power, bandwidth and reconfigurable nature.
High-Performance DSL (Digital Subscriber Line Technology) DSL
Technology
are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed. base-stations, voice compression, software-defined radio, highperformance embedded telecom and datacom applications, xDSL concentrators, fixed wireless local loop, multichannel voice compression, multiprotocol packet and cell processing protocols. Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk.