ASIP cho x l tn hiu

(Application-Specific Instruction Processor)

TS. Nguyn c Minh

Mc tiu

Cc thit b thng tin di ng cn:

Kch thc nh Gi thnh thp Tiu th t nng lng

Cn ti u MOPS/Watt v MOPS/mm2 (s php ton trn 1 giy trn 1 watt hoc trn 1mm2) m bo linh hot gip gim gi thnh

HUST-FET, 27/05/2012

So snh hiu qu tnh ton v linh hot

Ngun: T.Noll, RWTH Aachen

HUST-FET, 27/05/2012

So snh hiu qu tnh ton v linh hot

Ngun: Advanced Computer Architecture Laboratory, University of Michigan 4

HUST-FET, 27/05/2012

Nguyn tc c bn

X l tn hiu da trn mt s t cc thut ton c bn. Cc thut ton c bn chim khi lng ln trong yu cu tnh ton Ti u cc thut ton c bn trong x l tn hiu bng cc ch th (instructions) ph hp

HUST-FET, 27/05/2012

Mt s thut ton c bn c th trin khai

Butterfly unit
Viterbi decoder MAP decoder FFT

Eigenvalue decomposition (EVD)

MUSIC Delay acquisition MIMO Tx processing

Matrix-Matrix & Matrix-Vector Multiplication

MIMO processing (Rx & Tx)

LMMSE channel estimation (OFDM & MIMO) Iterative (Turbo) Decoding

CORDIC
Frequency offset estimation (e.g. AFC)

Phase synchronization OFDM post-FFT synchronization (sampling clock, fine frequency)

FFT & IFFT (spectral processing)

OFDM

Speech post processing (noise suppression) Image processing (not FFT but DCT)

HUST-FET, 27/05/2012

Electronic System Level Design

TS. Nguyn c Minh TS. ng Quang Hiu ThS. Trn Mnh Hong

HUST-FET, 27/05/2012

Outline

Design Flow Hardware Design Manpower Design Cost

HUST-FET, 27/05/2012

Electronic System Level Design Flow

Ngun: International Technology Roadmap for Semiconductors 2009 9

HUST-FET, 27/05/2012

Design Steps and Manpower

5-10 YEARS

Source: http://www.soccentral.com/

10

HUST-FET, 27/05/2012

Electronic System Level Cost

Software Costs > Design and Verification Costs >> Manufacturing Design makes products different

Ngun: International Business Strategy 2009

11

HUST-FET, 27/05/2012

System-on-Chip Design and Verification

12

HUST-FET, 27/05/2012

Experimental Design Flow

SOPC Builder
Processor Library Configure Processor Select & Configure Perigherals, IP p Conect Block Custom Instructions

Peripheral Library

IP Modules

Quartus II
User Design Other IP Block

Nios II IDE
HDL Source Files Generate C++ file Custom Library Peripheral Driver Verifacation & Debug

Synthesis& Fitter

Compiler,Linker,Debugger

Atera FPGA

13

HUST-FET, 27/05/2012