INTRODUCTION

Error detection and correction is found in many high-reliability and performance applications. For example, in enterprise data storage systems, memory caches are utilized to improvesystem reliability. The cache is typically placed inside the controller between the host interfacesand the disk array. A robust cache memory design often includes ECC functions to avoid single point of failure losses of customer data. ECC becomes an important feature for manycommunication applications, such as satellite receivers; it is more performance and costefficient to correct an error rather than retransmit the data.

Hamming code
The ECC functions described in this application note are made possible by Hamming code, arelatively simple yet powerful ECC code. It involves transmitting data with multiple check bits (parity) and decoding the associated check bits when receiving data to detect errors. The check bits are parallel parity bits generated from XORing certain bits in the original dataword. If bit error(s) are introduced in the codeword, several check bits show parity errors after decoding the retrieved codeword. The combination of these check bit errors display the nature of the error. In addition, the position of any single bit error is identified from the check bits.

Hamming diagram

For (7,4)

p1,p2,p3-parity bits p4-overall parity bit d-data bits

SECDED Codes
(single error correcting and double error detecting)

Algorithm
Assume a H-matrix
1 0 0 1 0 0 1 0 1 1 1

H =

0 0 1 1 0 1 1 1 1 0

Say we have the received vector: r = r0 r1 r2 r3 r4 r5 r6 We get syndrome vector as: S = r.H(transpose)

Cont.
We get syndrome as: s0 s1 s2 s0 =r0 + r3 +r5 +r6 s1 = r1 + r3 +r4 +r5 s2 = r2 + r4 + r5 + r6
:

Cont..
We get error pattern against syndromes:

Cont.
Now : r + e = v(corrected codeword) if it is equal to transmitted codeword,then single error has occurred. If it is different from the transmitted codeword,then there are multiple errors.

Decoding circuit for (7,4)

SECDED code
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY secded2 IS PORT( c4,c2,c1,d4,d3,d2,d1,pp : IN std_logic; o7,o6,o5,o4,o3,o2,o1,dd: INOUT std_logic); END ENTITY secded2 ;

ARCHITECTURE secdedarch OF secded2 IS signal s1: std_logic; signal s2: std_logic; signal s3: std_logic; signal errorpos1: std_logic; signal errorpos2: std_logic; signal errorpos3: std_logic; signal errorpos4: std_logic;

Code
signal errorpos5: std_logic; signal errorpos6: std_logic; signal errorpos7: std_logic; signal ddchk: std_logic; BEGIN ddchk <= c4 xor c2 xor c1 xor d4 xor d3 xor d2 xor d1 xor pp; s1<=c4 xor d4 xor d2 xor d1; s2<=c2 xor d4 xor d3 xor d2; s3<=c1 xor d3 xor d2 xor d1; dd <= (not(ddchk)) and ( s1 or s2 or s3); errorpos1<= s1 and (not(s2)) and s3; -- 100 errorpos2<= s1 and s2 and s3; -- 010 errorpos3<= (not(s1)) and s2 and s3; -- 110 errorpos4<= s1 and s2 and (not(s3)); --001

Code.
errorpos5<= (not(s1)) and (not(s2)) and s3; errorpos6<= (not(s1)) and s2 and (not(s3)); errorpos7<= s1 and (not(s2)) and (not(s3)); --111 o1<= d1 xor errorpos1; o2<= d2 xor errorpos2; o3<= d3 xor errorpos3; o4<= d4 xor errorpos4; o5<= c1 xor errorpos5; o6<= c2 xor errorpos6; o7<= c4 xor errorpos7; END secdedarch; --101 --011

THANK YOU..