Lecture 1

Introduction to Digital Design Methodology Engr. Toseef Abid

Introduction to Digital Design Methodology

Classical methods relied on schematics and manual methods of design. Modern design is based on computer languages by which design capability is enhanced in size and complexity. With manual method it is impossible to design ICs with several million gates With Hardware descriptive languages (HDL), effective and optimized design is manageable. Language based designs are - Portable - Independent of IC technologies - Better performance can be synthesized from an original HDL based model as the devices evolve with time.

HDLs

Convenient way to integrate Intellectual Property, Different source Proprietary Design Common design language, net reduction in design time. Automatic synthesis form a language based description which bypasses the tedious manual design. Dominant design paradigm, Designer built software prototype/model verify its functionality and then use a synthesis tool to automatically optimize the circuit. Synthesis tool focuses on functionality rather then on individual transistor or gate. Key point to work on are functionality, area and performance constraints Different architectures can be generated from the single HDL module and can be compared. Fundamentals models are referred to as the behavioral models HDL provides platform for tools like design entry, design verification, test generation, fault analysis simulation, timing analysis and /or verification, synthesis and automatic generation of schematic. Two languages Verilog and VHDL for digital and Spice for analog Hybrid language like Verilog-A for mixed signal circuits. System level design language is systemC and superlog

Design Methodologies
A systematic approach to minimize faults in ASIC and FPGA design This approach specifies a sequence of steps for design, Verify, synthesize and test a Digital circuit. Timing closers is attained when all of the signal path in the design satisfy the timing constraints imposed by the interface circuitry, the sequential elements and the system clock. The design of standard cell based ASIC are more complex as compared to FPGA

Design Specifications
An Elaborated statement of Functionality Timing Silicon area Power consumption Testability Fault coverage Other fanatical constraints etc

Description of a Sequential Machine State transition Chart Timing Chart

Algorithmic state machine Chart

Design Partition
Large circuits divided in to partitions to form an architecture with many blocks. Each block has its behavioral Model Top Down Approach or hieratical design Blocks are linked to conform the overall functionality Blocks are simpler then the whole system. The whole system cannot be synthesized but individual blocks can be in a reasonable amount of time

Design Entry
Language based description of the design and saving in electrical format. Saves time Difference between Top down and bottom up approach. Synthesis tool its self will find alternative realizations of the same function and generate repots describing the attributes of the design

HDL Based Designs

Are easier to debug then schematic. Incorporates documentation within the design like descriptive names, Comments, there for ease to understand.

Behavioral Designs
Is like the definition of a device. It discusses the functionality of the device not how to build it in hardware. It specifies the inputs the outputs and the relations between them. Rapid prototype design Verification of functionality and Optimization and mapping device in selected technology by using synthesis

Its advantages are

Synthesis tool

Synthesis tool creates an optimal internal representation of a circuit before mapping the description into the target technology Generic internal Database so, migration of design from different technologies is possible. At the operation of synthesis the tool removes redundant logics performs tradeoff between alternative architectures and/or multi-level equivalent circuits and ultimately achieve a design that is compatible with area and timing constraints

Simulation / Functional Verification

Design verification by simulation Three steps Development of test plan Test plan documentation development to test the functionality. ALU Test plan of combinational machine is simpler then the sequential machine (Larger no of states) Identification of
Stimulus Generator Response monitor Gold standard response

Development of test bench Is a module (Stimulus) in which

UUT is represented Input patterns Graphical display Response monitor

Document to observe the gules of the module created Execution of the test
Test bench is executed according to the test plan and two results might emerge
Correct Incorrect
Errors in the design Confirming the syntax Verify style conventions Eliminate barriers to synthesis

There is no point in moving forward before the proper execution of this step.

Design integration and verification

The same as simulation and functional verification just with the difference that the design is integrated and checked as a whole The test bench created in this will have focus on the top level block inputs and outputs

Pre-synthesis
A demonstration of full functionality is to be provided by the test bench, and any discrepancies between the functionality of Verilog behavioral model and the design specifications must be resolved Sign-off occurs after all known functionality error have been eliminated

Gate Level Synthesis and technology mapping

After all errors have been eliminated the synthesis tool creates an optimal boolean description and compose it in an available technology Synthesis Removes redundant logic Reduce the area of the implementation Satisfy speed specifications

It produces a netlist of standard cells or a database that will configure a target FPGA

Post-Synthesis
Design Validation A comparison of the synthesized gate level description and the behavioral Model. Both models are driven by the same Stimulus and the output (software or graphical is monitored, and are suppose to be the same. If however they are not work must be done to remove the discrepancies

Post-Synthesis
Timing Verification This is to check that the circuit meet the timing constraints and verify the speed at critical paths. Capacitance due to inter connection between the architecture Static timing analysis to verify longest path do not violate the timing constraints Re-synthesis might be required to meet the requirements in which we need to change the following parameters. Transistor Sizing Architecture Device substitution

Test Generation and fault simulation

A set of test vectors is applied to check the response. Testing considers process induces faults not the design faults. Design faults are supposed to be detected before Pre-synthesis sign out Might need to construct additional special circuits to test the ASIC as it might have billions of transistors but few hundred package pins.

Placement and routing

Placement of different cells to reduce disturbance in the interconnection architecture. Placement of different traces to reduces inductive and capacitive behavior in the circuit Clock Tree to provide skew-free distribution of the clock

Physical And Electrical Constraints

Physical Material width Corners Turning angle Loops and inductance (Just check) Parallel lines and capacitance (Just checked) Electrical Fan out Signal Integrity Crosstalk Power grid drop Noise level Heat constraints

Parasitic Extraction
Parasitic Capacitance and inductance are extracted by a tool and is used to calculate accurate output characteristics and timing performances

After all checks of functionality and timing closer the mask set is ready for fabrication GDS II format